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    Semiconductor device
    3.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20110121294A1

    公开(公告)日：2011-05-26

    申请号：US12926293

    申请日：2010-11-08

    申请人： Takahiro Koyama ,  Sadayuki Okuma

    发明人： Takahiro Koyama ,  Sadayuki Okuma

    IPC分类号： H01L23/48

    CPC分类号： G01R31/2644 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  G11C2029/2602 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

    摘要： A semiconductor device includes a plurality of first data input/output terminals, a plurality of second data input/output terminals, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip includes a plurality of first data input/output pads connected with the first data input/output terminals, a first test circuit, and a first memory portion. The first test circuit generates a first test result in response to a data output from the first memory portion at a test operation. The second semiconductor chip includes a plurality of second data input/output pads connected with the second data input/output terminals, a second and a third test circuits, and a second memory portion. The second test circuit generates a second test result in response to a data output from the second memory portion, and the third test circuit generates a third test result in response to the second test result and the first test result input from the first test circuit of the first semiconductor chip and outputs the third test result from a specified second data input/output terminal.

    摘要翻译： 半导体器件包括多个第一数据输入/输出端子，多个第二数据输入/输出端子，第一半导体芯片和第二半导体芯片。 第一半导体芯片包括与第一数据输入/输出端子连接的多个第一数据输入/输出焊盘，第一测试电路和第一存储器部分。 第一测试电路在测试操作时响应于从第一存储器部分输出的数据产生第一测试结果。 第二半导体芯片包括与第二数据输入/输出端子连接的多个第二数据输入/输出焊盘，第二和第三测试电路以及第二存储器部分。 第二测试电路响应于从第二存储器部分输出的数据产生第二测试结果，并且第三测试电路响应于第二测试结果和从第一测试电路输入的第一测试结果产生第三测试结果 第一半导体芯片，并从指定的第二数据输入/输出端输出第三测试结果。

    Semiconductor memory device including a repair circuit which includes mode fuses
    5.
    发明授权
    Semiconductor memory device including a repair circuit which includes mode fuses 有权
    半导体存储器件包括包括模式保险丝的修复电路

    公开(公告)号：US07826295B2

    公开(公告)日：2010-11-02

    申请号：US12076063

    申请日：2008-03-13

    申请人： Atsushi Masumizu ,  Sadayuki Okuma

    发明人： Atsushi Masumizu ,  Sadayuki Okuma

    IPC分类号： G11C17/18

    CPC分类号： G11C29/84 ,  G11C29/787

    摘要： In a semiconductor memory device, a repair circuit includes mode fuses to select one of plural repair modes corresponding to plural kinds of defects, respectively. The semiconductor memory device can repair a defective memory cell having operational margin defect without using redundancy memory cells.

    摘要翻译： 在半导体存储器件中，修复电路包括分别对应于多种缺陷的多种修复模式之一选择模式熔丝。 半导体存储器件可以在不使用冗余存储单元的情况下修复具有操作余量缺陷的缺陷存储单元。

    Apparatus and method for creating circuit diagram, program therefor and recording medium storing the program
    6.
    发明授权
    Apparatus and method for creating circuit diagram, program therefor and recording medium storing the program 失效
    用于创建电路图，其程序和存储程序的记录介质的装置和方法

    公开(公告)号：US07676770B2

    公开(公告)日：2010-03-09

    申请号：US11086532

    申请日：2005-03-23

    申请人： Sadayuki Okuma

    发明人： Sadayuki Okuma

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/509 ,  G06F17/5045 ,  G06F2217/74

    摘要： It is an object of the present invention to realize a circuit diagram creating method and circuit diagram creating apparatus capable of efficiently acquiring information on a lower layer, and a circuit diagram creating method for creating a layered electric circuit diagram from data indicating an electric circuit that includes the steps of determining an outline area to be displayed from wiring information and graphics information which are data indicating the electric circuit for symbol graphics of a lower layer and displaying information on the circuit diagram so as not to go beyond the outline area.

    摘要翻译： 本发明的目的是实现一种能够有效地获取下层信息的电路图创建方法和电路图创建装置，以及用于从表示电路的数据产生分层电路图的电路图创建方法， 包括以下步骤：从布线信息和图形信息确定要显示的轮廓区域，所述图形信息是指示下层符号图形的电路的数据，并且显示关于电路图的信息，以便不超过轮廓区域。

    Semiconductor memory device
    7.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20080225620A1

    公开(公告)日：2008-09-18

    申请号：US12076063

    申请日：2008-03-13

    申请人： Atsushi Masumizu ,  Sadayuki Okuma

    发明人： Atsushi Masumizu ,  Sadayuki Okuma

    IPC分类号： G11C17/18

    CPC分类号： G11C29/84 ,  G11C29/787

    摘要： In a semiconductor memory device, a repair circuit includes mode fuses to select one of plural repair modes corresponding to plural kinds of defects, respectively. The semiconductor memory device can repair a defective memory cell having operational margin defect without using redundancy memory cells.

    摘要翻译： 在半导体存储器件中，修复电路包括分别对应于多种缺陷的多种修复模式之一选择模式熔丝。 半导体存储器件可以在不使用冗余存储单元的情况下修复具有操作余量缺陷的缺陷存储单元。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06496403B2

    公开(公告)日：2002-12-17

    申请号：US09906809

    申请日：2001-07-18

    申请人： Hiromasa Noda ,  Sadayuki Okuma ,  Hiroshi Ichikawa ,  Hiroki Miyashita ,  Yasushi Takahashi

    发明人： Hiromasa Noda ,  Sadayuki Okuma ,  Hiroshi Ichikawa ,  Hiroki Miyashita ,  Yasushi Takahashi

    IPC分类号： G11C506

    CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

    摘要： Disclosed a semiconductor memory device in which an access to a memory cell is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output. The semiconductor memory device includes: a first input circuit having input capacitance corresponding to the input terminal to which the command is input; and a second input circuit having input capacitance corresponding to the data terminal. A mask signal for checking the write signal input from the data terminal is input by either the first or second input circuit by a bonding option technique.

    摘要翻译： 公开了一种半导体存储器件，其中根据命令指定对存储单元的访问，并且公共数据端用作输入到存储单元的写入信号的输入端子以及从其读取的输出端子 输出来自存储单元的信号。 半导体存储器件包括：第一输入电路，其具有与输入端相对应的输入电容; 以及具有与数据端子对应的输入电容的第二输入电路。 用于检查从数据终端输入的写入信号的掩码信号由第一或第二输入电路通过接合选项技术输入。

    Semiconductor device and test method thereof
    10.
    发明授权
    Semiconductor device and test method thereof 有权
    半导体器件及其测试方法

    公开(公告)号：US08958258B2

    公开(公告)日：2015-02-17

    申请号：US13182140

    申请日：2011-07-13

    申请人： Sadayuki Okuma

    发明人： Sadayuki Okuma

    IPC分类号： G11C29/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/4099 ,  G11C8/14 ,  G11C11/408 ,  G11C29/02 ,  G11C29/24 ,  G11C29/12

    CPC分类号： G11C11/4099 ,  G11C8/14 ,  G11C11/4085 ,  G11C29/02 ,  G11C29/025 ,  G11C29/24 ,  G11C2029/1202

    摘要： A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word lines, each of which is sandwiched between two corresponding ones of the word lines; a main dummy word line to which the dummy word lines included in the memory mats are commonly electrically connected; and a dummy-word-line control circuit that detects an electric potential of the main dummy word line when a test signal is activated, and outputs an error signal when the electric potential exceeds a predetermined threshold value. According to the present invention, because an electric potential of each of the dummy word lines is directly detected, an address of the word line, which has a short circuit with the dummy word line, can be reliably detected in a short time.

    摘要翻译： 半导体器件包括多个存储器衬垫，每个存储器衬垫包括多个字线，多个位线，布置在字线和位线的交点处的多个存储器单元，以及多个虚拟 字线，其中每一行都夹在两条对应的字线之间; 包含在存储器垫中的虚拟字线通常电连接到的主虚拟字线; 以及伪字线控制电路，其在测试信号被激活时检测主虚拟字线的电位，并且当电位超过预定阈值时输出误差信号。 根据本发明，由于直接检测出每个虚拟字线的电位，所以能够在短时间内可靠地检测出与虚拟字线短路的字线的地址。