公开(公告)号：US08299580B2

公开(公告)日：2012-10-30

申请号：US12712921

申请日：2010-02-25

申请人： Takahiro Kumakawa ,  Hideki Kojima ,  Tomoaki Furukawa

发明人： Takahiro Kumakawa ,  Hideki Kojima ,  Tomoaki Furukawa

IPC分类号： H01L23/544

CPC分类号： B23K26/40 ,  B23K26/53 ,  B23K2103/172 ,  B23K2103/50 ,  B28D5/0011

摘要： A semiconductor wafer includes a plurality of predetermined separation lines extending from an upper surface to a bottom surface; and a semiconductor substrate including a plurality of chip regions segmented by the predetermined separation lines. Tensile stress is applied to regions of the semiconductor substrate provided with the predetermined separation lines.

摘要翻译： 半导体晶片包括从上表面延伸到底表面的多个预定分隔线; 以及包括由所述预定分隔线分割的多个芯片区域的半导体衬底。 对具有预定分离线的半导体衬底的区域施加拉伸应力。

公开(公告)号：US07964475B2

公开(公告)日：2011-06-21

申请号：US11951441

申请日：2007-12-06

申请人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

发明人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

IPC分类号： H01L27/00 ,  H01L21/82

CPC分类号： H01L21/78

摘要： A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

摘要翻译： 在切割区域3的切割点的外侧形成改质层5和改质层8.因此，在切割点的不同物理性质之间不形成另一界面，可以防止从界面 在半导体元件2和半导体基板1之间以及在切割期间从半导体元件的表面，从而抑制了对半导体元件的切屑的发展。

公开(公告)号：US07808059B2

公开(公告)日：2010-10-05

申请号：US11797292

申请日：2007-05-02

申请人： Takahiro Kumakawa

发明人： Takahiro Kumakawa

IPC分类号： H01L29/78

CPC分类号： B81C1/00873 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/50 ,  H01L21/78

摘要： In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.

公开(公告)号：US20100015781A1

公开(公告)日：2010-01-21

申请号：US12570548

申请日：2009-09-30

申请人： Takahiro Kumakawa

发明人： Takahiro Kumakawa

IPC分类号： H01L21/304

CPC分类号： B81C1/00873 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/50 ,  H01L21/78

摘要： In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.

摘要翻译： 在半导体基板1中，具有隔膜结构的多个半导体元件2以单元格的形式在长度方向和横向方向上形成，并且V形槽3通过各向异性蚀刻连续形成，仅在分开线4上平行形成 一个方向，分离线4彼此正交并分别分开各个半导体元件2。

公开(公告)号：US20110108957A1

公开(公告)日：2011-05-12

申请号：US12926772

申请日：2010-12-08

申请人： Masaki Utsumi ,  Takahiro Kumakawa

发明人： Masaki Utsumi ,  Takahiro Kumakawa

IPC分类号： H01L23/544 ,  H01L21/302

CPC分类号： B23K26/60 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/50 ,  B28D5/0011 ,  H01L2924/10158 ,  H01L2924/16195 ,  H01L2924/16235

摘要： A semiconductor substrate (1) includes a plurality of semiconductor elements (2) in which functional elements are constructed and which is formed in a grid pattern, wherein continuous linear grooves (3) are formed on longitudinal and lateral separating lines (4) that individually separate the plurality of semiconductor elements (2) with the exception of intersections of the separating lines (4) and portions corresponding to corners of each semiconductor element (2).

摘要翻译： 半导体衬底（1）包括多个半导体元件（2），其中构成功能元件并且形成为格栅图案，其中连续的直线槽（3）分别形成在纵向和横向分隔线（4）上 除了分离线（4）的交点和对应于每个半导体元件（2）的角部的部分之外，分离多个半导体元件（2）。

公开(公告)号：US20070287215A1

公开(公告)日：2007-12-13

申请号：US11798676

申请日：2007-05-16

申请人： Masaki Utsumi ,  Takahiro Kumakawa ,  Masami Matsuura ,  Yoshihiro Matsushima

发明人： Masaki Utsumi ,  Takahiro Kumakawa ,  Masami Matsuura ,  Yoshihiro Matsushima

IPC分类号： H01L21/00

CPC分类号： B81C1/00896 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/50 ,  B81B2201/0257

摘要： A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer 101 to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film.

摘要翻译： 一种制造半导体器件的方法包括：在包括在半导体晶片中的多个芯片中的每一个的预定区域上形成振动膜的步骤（a）; 在半导体晶片上形成包含位于每个芯片的振动膜上的牺牲层的中间膜的步骤（b） 以及在中间膜上形成固定膜的步骤（c）。 该方法还包括在步骤（c）之后，对半导体晶片101进行刀片切割以分离芯片的步骤（d）和通过蚀刻去除牺牲层以提供空腔的步骤（e） 在振动膜和固定膜之间。

公开(公告)号：US06924173B2

公开(公告)日：2005-08-02

申请号：US10387457

申请日：2003-03-14

申请人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

发明人： Kazumi Watase ,  Hiroaki Fujimoto ,  Ryuichi Sahara ,  Nozomi Shimoishizaka ,  Takahiro Kumakawa ,  Kazuyuki Kaino ,  Yoshifumi Nakamura

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07 ,  H01L21/58

CPC分类号： H01L24/97 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49872 ,  H01L24/45 ,  H01L24/48 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.

摘要翻译： 公开了一种半导体器件10，其包括具有第一元件电极12的布置的第一半导体元件11，具有第二元件电极14的布置的第二半导体元件13，连接构件15，其将第一元件 电极12和第二元件电极14，覆盖第一半导体元件11的主表面11a和第二半导体元件13的背面13b的绝缘层17，形成在绝缘层17上的布线层22， 连接到暴露在开口部分21中的第一元件电极部分12b和形成为绝缘层17上的布线层22的一部分的外部电极23。

公开(公告)号：US06852616B2

公开(公告)日：2005-02-08

申请号：US10165279

申请日：2002-06-10

申请人： Ryuichi Sahara ,  Kazumi Watase ,  Takahiro Kumakawa ,  Kazuyuki Kainoh ,  Nozomi Shimoishizaka

发明人： Ryuichi Sahara ,  Kazumi Watase ,  Takahiro Kumakawa ,  Kazuyuki Kainoh ,  Nozomi Shimoishizaka

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/12 ,  H01L23/31 ,  H01L23/485 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/522 ,  H01L23/5227 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552 ,  H01L2924/013

摘要： A first element electrode and a second element electrode connected electrically to a semiconductor element on a substrate are formed, and then an insulating film is formed on the substrate including the element electrodes. Thereafter, a first opening for exposing the first element electrode and a second opening for exposing the second element electrode are formed on the insulating film. Then, a first external electrode connected to the first element electrode via the first opening is formed immediately above the first element electrode. Furthermore, a second external electrode and a connecting wire having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode are formed on the insulating film.

摘要翻译： 形成与基板上的半导体元件电连接的第一元件电极和第二元件电极，然后在包括元件电极的基板上形成绝缘膜。 此后，在绝缘膜上形成用于暴露第一元件电极的第一开口和用于暴露第二元件电极的第二开口。 然后，在第一元件电极的正上方形成有经由第一开口与第一元件电极连接的第一外部电极。 此外，在绝缘膜上形成第二外部电极和连接线，其一端经由第二开口连接到第二元件电极，而另一端连接到第二外部电极。

公开(公告)号：US07754584B2

公开(公告)日：2010-07-13

申请号：US12570548

申请日：2009-09-30

申请人： Takahiro Kumakawa

发明人： Takahiro Kumakawa

IPC分类号： H01L21/78 ,  H01L21/46 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L21/00 ,  H01L21/768

CPC分类号： B81C1/00873 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/50 ,  H01L21/78

摘要： In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.

摘要翻译： 在半导体基板1中，具有隔膜结构的多个半导体元件2以单元格的形式在长度方向和横向方向上形成，并且V形槽3通过各向异性蚀刻连续形成，仅在分开线4上平行形成 一个方向，分离线4彼此正交并分别分开各个半导体元件2。

公开(公告)号：US20080135975A1

公开(公告)日：2008-06-12

申请号：US11951441

申请日：2007-12-06

申请人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

发明人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

IPC分类号： H01L27/00 ,  H01L21/82

CPC分类号： H01L21/78

摘要： A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

摘要翻译： 在切割区域3的切割点的外部形成改质层5和改质层8。 因此，在切割点之间不形成不同物理特性之间的另一界面，可以防止在切割期间从半导体元件2和半导体基板1之间的界面以及半导体元件的表面沿着晶体取向进行切屑， 从而抑制了对半导体元件的切屑的发展。