公开(公告)号：US06229211B1

公开(公告)日：2001-05-08

申请号：US09362683

申请日：1999-07-29

申请人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

发明人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53209 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a base layer, a barrier metal layer formed on the base layer and a metal interconnect formed on the barrier metal layer, the barrier metal layer being made of at least one element &agr; selected from metal elements and at least one element &bgr; selected from a group of boron, oxygen, carbon and nitrogen and having at least two compound films &agr;&bgr;n with different compositional ratios in atomic level arranged to form a laminate. When the elements &agr; contained in the compound films &agr;&bgr;n are same and identical and at least one of the at least two compound films &agr;&bgr;n is a compound film &agr;&bgr;x (x>1), the via resistance and the interconnect resistance of the device can be reduced, while maintaining the high barrier effect.

摘要翻译： 半导体器件包括基底层，形成在基底层上的阻挡金属层和形成在阻挡金属层上的金属互连，阻挡金属层由选自金属元素和至少一个元素β的至少一种元素α制成 选自一组硼，氧，碳和氮，并且具有至少两个具有原子级别的不同组成比的英文字母复合膜，以形成层压体。 当复合薄膜字母表中包含的元素α相同且相同时，至少两个化合物薄膜字母表中的至少一个是化合物薄膜字母（x> 1）时，器件的通孔电阻和互连电阻可以减小 同时保持高屏障效果。

公开(公告)号：US06518177B1

公开(公告)日：2003-02-11

申请号：US09783561

申请日：2001-02-15

申请人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

发明人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53209 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is formed by a compound film &agr;&ggr;x made of at least one element &agr; selected from metal elements and at least one element &ggr; selected from the group consisting of boron, carbon, and nitrogen on a base layer containing oxygen (O), and forming a compound film &agr;&ggr;yOz by causing the compound film &agr;&ggr;x to reduce the base layer and thereby oxidizing the compound film &agr;&ggr;x on an interface of the compound film &agr;&ggr;x and the base layer, wherein each of x and y is a ratio of the number of atoms of the element &ggr; to the number of atoms of the element &agr;, and z is a ratio of the number of atoms of the oxygen to the number of atoms of the element &agr;.

摘要翻译： 通过由选自金属元素的至少一种元素α和在含氧（O）的基底层上选自硼，碳和氮的至少一种元素γ制成的化合物膜，形成半导体器件，以及 通过使化合物膜alphagammax减少基底层从而氧化化合物膜的碱性和底层的界面上的化合物膜，形成化合物膜alphagammayOz，其中x和y分别为原子数 元素γ与元素α的原子数之比，z是氧原子数与元素α原子数之比。

公开(公告)号：US06348402B1

公开(公告)日：2002-02-19

申请号：US09526880

申请日：2000-03-16

申请人： Takashi Kawanoue ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Tadashi Iijima

发明人： Takashi Kawanoue ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Tadashi Iijima

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A groove or hole is formed in an insulating layer formed on a semiconductor substrate, and a first conductive layer including a first metal element is formed on a surface of the insulating layer. By oxidizing the first conductive layer, an oxide layer of the first metal element is formed on a surface of the first conductive layer. A second conductive layer including a second metal element having a free energy of oxide formation lower than that of the first metal element is deposited thereon. By reducing the oxide layer of the first metal element by the second metal element, an oxide layer of the second metal element is formed at the interface between the first conductive layer and the second conductive layer. Further, an interconnection is buried in the groove or hole of the insulating layer. Thereby, a thin second metal oxide layer having excellent barrier properties against an interconnection material and excellent adhesion to the interconnection material can be selectively formed with a uniform thickness on the surface of the first conductive layer used as a barrier metal layer of the interconnection.

摘要翻译： 在形成于半导体衬底上的绝缘层中形成沟槽，在绝缘层的表面上形成包括第一金属元件的第一导电层。 通过氧化第一导电层，在第一导电层的表面上形成第一金属元素的氧化物层。 在其上沉积包括具有低于第一金属元素的自由能的氧化物形成的第二金属元素的第二导电层。 通过由第二金属元件还原第一金属元件的氧化物层，在第一导电层和第二导电层之间的界面处形成第二金属元素的氧化物层。 此外，互连被埋在绝缘层的凹槽或孔中。 由此，可以在用作互连的阻挡金属层的第一导电层的表面上选择性地形成具有优良的互连材料阻隔性和对互连材料的优异粘附性的薄的第二金属氧化物层。

公开(公告)号：US07575664B2

公开(公告)日：2009-08-18

申请号：US11135328

申请日：2005-05-24

申请人： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

发明人： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

IPC分类号： C25D21/12

CPC分类号： C25D5/16 ,  C25D5/02 ,  C25D5/06 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

摘要： A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

摘要翻译： 对形成在具有凹陷图案的基板上的导电层施加阴极电位。 将与阳极电接触的电镀溶液供给到导电层，以在导电层上形成镀膜。 此时，通过使包含电镀液的浸渍部件面对导电层而供给电镀液。 由于电镀溶液滞留在凹陷中，所以与基板的上表面相比，供给电镀液的量较多，因此抑制了镀膜的镀覆速度。 因此，可以在诸如凹槽或孔的凹陷中优先地形成镀膜。

公开(公告)号：US20080251385A1

公开(公告)日：2008-10-16

申请号：US12116562

申请日：2008-05-07

申请人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

发明人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

IPC分类号： C25D21/12

CPC分类号： H01L21/6719 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  C25D17/14 ,  H01L21/2885 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/6723 ,  H01L21/76877 ,  H01L21/76879 ,  H01L2924/0002 ,  H05K3/423 ,  H01L2924/00

摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

摘要翻译： 用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。 该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。 密封材料90接触表面的周缘部分，以水密的方式密封该部分。 阴极电极88在与基板接触时通过电流。 阴极部38与基板保持部36一体旋转。 电极臂部分30在阴极部分38的上方并且可水平和垂直地移动，并且阳极98面向下。 将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。 因此，电镀处理和附带的处理可以通过单个单元进行。

公开(公告)号：US06998342B2

公开(公告)日：2006-02-14

申请号：US10835319

申请日：2004-04-30

申请人： Tetsuo Matsuda ,  Hiroshi Toyoda ,  Hisashi Kaneko

发明人： Tetsuo Matsuda ,  Hiroshi Toyoda ,  Hisashi Kaneko

IPC分类号： H01L21/44

CPC分类号： H01L21/76874 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/405 ,  C23C18/54 ,  C23C28/00 ,  C25D7/123 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/76867 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.

公开(公告)号：US06632335B2

公开(公告)日：2003-10-14

申请号：US09742110

申请日：2000-12-22

申请人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

发明人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

IPC分类号： C25D2112

CPC分类号： H01L21/6719 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  C25D17/14 ,  H01L21/2885 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/6723 ,  H01L21/76877 ,  H01L21/76879 ,  H01L2924/0002 ,  H05K3/423 ,  H01L2924/00

摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

摘要翻译： 用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。 该装置具有将待镀表面向上水平保持并旋转的衬底的衬底保持部分 36 。 密封材料 90 接触表面的外围边缘部分，以水密的方式密封该部分。 当与基板接触时，阴极电极 88 通过电流。 阴极部分 38 与衬底保持部分 36 整体旋转。 电极臂部分 30 在阴极部分 38 之上，水平和垂直移动并具有阳极 PDAT> 98 面朝下。 将电镀液倒入要被镀表面和靠近待镀表面的阳极 98 之间的空间中。 因此，电镀处理和附带的处理可以通过单个单元执行

公开(公告)号：US06579785B2

公开(公告)日：2003-06-17

申请号：US09767724

申请日：2001-01-24

申请人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

发明人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在绝缘层上形成中间层，在中间层中形成沟槽和绝缘层，在中间层上形成第一阻挡层，在其上沉积布线层 第一阻挡层，从而使布线层填充沟槽，对布线层进行平坦化处理，去除布线的表面部分，从而允许布线的表面比绝缘层的表面凹陷，因此 形成凹部，在所述中间层和所述凹部的内壁上形成第二阻挡层，对所述第二阻挡层进行平坦化处理，从而选择性地除去所述中间层，使所述绝缘层露出。

公开(公告)号：US06403481B1

公开(公告)日：2002-06-11

申请号：US09371221

申请日：1999-08-10

申请人： Tetsuo Matsuda ,  Hisashi Kaneko

发明人： Tetsuo Matsuda ,  Hisashi Kaneko

IPC分类号： H01L214763

CPC分类号： H01L21/76858 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886 ,  H01L2221/1089

摘要： A film formation method for manufacture of a semiconductor device includes the steps of forming a first metal film as a continuous film on a substrate, forming a second metal film as discontinuous films on the substrate formed with the first metal film, and forming a third metal film by plating on the substrate formed with the first and second metal films.

摘要翻译： 用于制造半导体器件的成膜方法包括以下步骤：在基板上形成作为连续膜的第一金属膜，在形成有第一金属膜的基板上形成作为不连续膜的第二金属膜，以及形成第三金属 通过在由第一和第二金属膜形成的基板上电镀。

公开(公告)号：US07387717B2

公开(公告)日：2008-06-17

申请号：US10631726

申请日：2003-08-01

申请人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

发明人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

IPC分类号： C25D7/12

CPC分类号： H01L21/6719 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  C25D17/14 ,  H01L21/2885 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/6723 ,  H01L21/76877 ,  H01L21/76879 ,  H01L2924/0002 ,  H05K3/423 ,  H01L2924/00

摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

摘要翻译： 用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。 该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。 密封材料90接触表面的周缘部分，以水密的方式密封该部分。 阴极电极88在与基板接触时通过电流。 阴极部38与基板保持部36一体地旋转。电极臂部30在阴极部38的上方，水平且垂直地移动，阳极98面朝下。 将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。 因此，电镀处理和附带的处理可以通过单个单元进行。