公开(公告)号：US06313533B1

公开(公告)日：2001-11-06

申请号：US09346949

申请日：1999-07-01

申请人： Takuo Funaya ,  Kouji Matsui ,  Naoji Senba

发明人： Takuo Funaya ,  Kouji Matsui ,  Naoji Senba

IPC分类号： H01L2348

CPC分类号： H01L24/81 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05571 ,  H01L2224/10165 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/29011 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/00 ,  H01L2924/00012

摘要： There is provided a function element including a resin layer formed on a surface thereof, the resin layer having adhesive property and sealing property, the resin layer having such a pattern that a resin layer does not exist in at least one of following areas: (a) a first area around an area where device performances are influenced by resin of which the resin layer was composed, (b) a second area around pads or bumps, (c) a third area around an area on which a wiring of a substrate will exist when the function element is coupled to the substrate, and (d) a fourth area around an area on which a passive element mounted on a substrate will exist when the function element is coupled to the substrate. The function element prevents extra resin from adhering to an area of the function element where device performances will be influenced by the resin, when the function element is coupled to a substrate with a resin layer being sandwiched therebetween.

摘要翻译： 提供了一种功能元件，其包括在其表面上形成的树脂层，具有粘合性和密封性的树脂层，树脂层具有在以下至少一个区域中不存在树脂层的图案：（a ）围绕着构成树脂层的树脂影响的区域周围的第一区域，（b）围绕焊盘或凸块的第二区域，（c）在基板的布线的区域周围的第三区域 当功能元件耦合到衬底时存在，以及（d）当功能元件耦合到衬底时，围绕安装在衬底上的无源元件将存在的区域周围的第四区域。 当功能元件与夹在其间的树脂层的基板耦合时，功能元件防止额外的树脂粘附到功能元件的其中器件性能将受树脂影响的区域。

公开(公告)号：US08198140B2

公开(公告)日：2012-06-12

申请号：US12882277

申请日：2010-09-15

申请人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

发明人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/061 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

摘要翻译： 用于安装半导体的布线基板设置有绝缘膜，形成在绝缘膜中的布线以及通过通孔电连接到导线的多个电极垫。 电极焊盘被设置为使其表面暴露于绝缘膜的前表面和后表面，并且电极焊盘的侧表面的至少一部分被埋在绝缘膜中。 绝缘膜通过在相应的两个金属板上形成电极焊盘而形成，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘，并将绝缘层彼此粘合在一起，然后除去 金属板。

公开(公告)号：US20060012048A1

公开(公告)日：2006-01-19

申请号：US11174526

申请日：2005-07-06

申请人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

发明人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

IPC分类号： H01L23/48

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/061 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

摘要翻译： 用于安装半导体的布线基板设置有绝缘膜，形成在绝缘膜中的布线以及通过通孔电连接到导线的多个电极垫。 电极焊盘被设置为使其表面暴露于绝缘膜的前表面和后表面，并且电极焊盘的侧表面的至少一部分被埋在绝缘膜中。 绝缘膜通过在相应的两个金属板上形成电极焊盘而形成，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘，并将绝缘层彼此粘合在一起，然后除去 金属板。

公开(公告)号：US07816782B2

公开(公告)日：2010-10-19

申请号：US11174526

申请日：2005-07-06

申请人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

发明人： Hideya Murai ,  Tadanori Shimoto ,  Takuo Funaya ,  Katsumi Kikuchi ,  Shintaro Yamamichi ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata ,  Kouji Matsui ,  Shinichi Miyazaki

IPC分类号： H01L23/14 ,  H01L23/12

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/061 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

摘要翻译： 用于安装半导体的布线基板设置有绝缘膜，形成在绝缘膜中的布线以及通过通孔电连接到导线的多个电极垫。 电极焊盘被设置为使其表面暴露于绝缘膜的前表面和后表面，并且电极焊盘的侧表面的至少一部分被埋在绝缘膜中。 绝缘膜通过在相应的两个金属板上形成电极焊盘而形成，然后在相应的金属板上层叠绝缘层和电线以覆盖电极焊盘，并将绝缘层彼此粘合在一起，然后除去 金属板。

公开(公告)号：US06662442B1

公开(公告)日：2003-12-16

申请号：US09619502

申请日：2000-07-19

申请人： Kouji Matsui ,  Kazunori Mune ,  Hirofumi Fujii ,  Satoshi Tanigawa

发明人： Kouji Matsui ,  Kazunori Mune ,  Hirofumi Fujii ,  Satoshi Tanigawa

IPC分类号： H01K310

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L2221/68345 ,  H01L2924/15311 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A process for producing a printed wiring board, particularly an interposer for a chip size package, which comprises the steps of (1) forming an outer insulator layer 22 having outer via-holes 24 on a substrate 32, (2) forming conducting passages 31 through the outer via-holes 24 by plating with metal up to substantially the same level as the upper surface of the outer insulator layer 22, (3) forming a thin metal film 29 on the outer insulator layer 22 and on the conducting passages 31, (4) forming a conductor layer 21 in a prescribed circuit pattern on the thin metal film 29 by plating, (5) removing the part of the thin metal film 29 on which the conductor layer 21 is not formed, (6) forming an inner insulator layer 23 on the conductor layer 21, and (7) removing the substrate 32. The outer insulator layer is formed with flatness to secure good adhesion to a semiconductor chip.

摘要翻译： 一种用于制造印刷线路板的方法，特别是用于芯片尺寸封装的插入件，其包括以下步骤：（1）在基板32上形成具有外部通孔24的外部绝缘体层22，（2）形成导电通路31 通过用外部绝缘体层22的上表面大致相同的金属镀覆外部通孔24，（3）在外绝缘体层22和导电路31上形成薄金属膜29， （4）通过电镀在薄金属膜29上形成规定的电路图案的导体层21，（5）除去未形成导体层21的金属薄膜29的一部分，（6）形成内部 导体层21上的绝缘体层23，以及（7）去除衬底32.外绝缘层形成为平坦度，以确保对半导体芯片的良好粘合性。

公开(公告)号：US06618694B1

公开(公告)日：2003-09-09

申请号：US09084108

申请日：1998-05-26

申请人： Akinobu Shibuya ,  Kouji Matsui ,  Hidehito Matsuyama

发明人： Akinobu Shibuya ,  Kouji Matsui ,  Hidehito Matsuyama

IPC分类号： G06F1750

CPC分类号： G06T17/20 ,  G06F17/5018 ,  G06F2217/80

摘要： A user uses part data forming means 101 and module data forming means 102 to input the actual dimension, physical constants and mesh dividing number for fundamental shapes which are registered in advance, thereby forming parts, and then indicates the relative position between the parts to form the entire shape of an assembly of plural parts without paying attention to coincidence or non-coincidence of nodal points. Data converting means 104 divides the shape of each part thus assembled according to the indicated mesh divisional number to generate element data and nodal point data. Further, it generates a constraint equation for connecting nodal points which are non-connected between neighboring parts, and forms an analysis model 401. A finite element method analyzer 105 uses approximate calculation means 106 to approximate a non-connected nodal point displacement from a nodal point displacement of neighboring structural elements on the basis of the constraint equation.

摘要翻译： 用户使用部件数据形成装置101和模块数据形成装置102输入预先登记的基本形状的实际尺寸，物理常数和网格划分数，从而形成零件，然后指示部件之间的相对位置，以形成 多个部分的组合的整体形状，而不注意节点的巧合或非重合。 数据转换装置104根据指示的网格划分数来划分如此组装的每个部分的形状，以生成元素数据和节点数据。 此外，它产生用于连接在相邻部分之间不连接的节点的约束方程，并且形成分析模型401.有限元方法分析器105使用近似计算装置106近似来自节点的非连接节点位移 基于约束方程的相邻结构元素的点位移。