公开(公告)号：US5449411A

公开(公告)日：1995-09-12

申请号：US137974

申请日：1993-10-19

申请人： Takuya Fukuda ,  Junji Sato ,  Fumiyuki Kanai ,  Atsushi Tsuchiya

发明人： Takuya Fukuda ,  Junji Sato ,  Fumiyuki Kanai ,  Atsushi Tsuchiya

IPC分类号： C23C16/50 ,  C23C16/44 ,  C23C16/511 ,  H01J37/32 ,  H01L21/205 ,  H01L21/31 ,  C23C16/30

CPC分类号： H01J37/32862 ,  C23C16/4405 ,  C23C16/511 ,  Y10S156/916

摘要： A microwave plasma processing apparatus is provided with a vacuum chamber, a substrate holder for mounting a substrate to be processed, a reactive gas feed port, a cleaning gas feed port, a plasma generation device for generating a processing plasma from the reactive gas and a cleaning plasma from the cleaning gas, and a high-frequency electric field application device for applying an electric field having a frequency that allows ions in the cleaning plasma to follow changes in the electric field. The high-frequency electric field application device is activated to apply the electric field to the cleaning plasma so as to remove substances that have been deposited on the surfaces of the vacuum chamber and substrate holder due to the processing of the substrate by the processing plasma, thereby cleaning up the vacuum chamber and substrate holder.

摘要翻译： 微波等离子体处理装置设置有真空室，用于安装待处理基板的基板保持器，反应气体供给口，清洁气体供给口，用于从反应性气体产生处理等离子体的等离子体产生装置，以及 从清洁气体中清洗等离子体;以及高频电场施加装置，用于施加具有允许清洗等离子体中的离子跟随电场变化的频率的电场。 高频电场施加装置被激活以将电场施加到清洁等离子体，以便通过处理等离子体处理基板来除去沉积在真空室和基板保持器的表面上的物质， 从而清洁真空室和基板保持器。

公开(公告)号：US5347100A

公开(公告)日：1994-09-13

申请号：US857658

申请日：1992-03-26

申请人： Takuya Fukuda ,  Michio Ohue ,  Fumiyuki Kanai ,  Atsuyoshi Koike ,  Katsuaki Saito ,  Kazuo Suzuki

发明人： Takuya Fukuda ,  Michio Ohue ,  Fumiyuki Kanai ,  Atsuyoshi Koike ,  Katsuaki Saito ,  Kazuo Suzuki

IPC分类号： H01L21/768 ,  H01L23/532 ,  B23K9/00 ,  B44C1/22

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  H01L23/5329 ,  H01L2924/0002

摘要： Disclosed are a semiconductor device comprising a semiconductor substrate, a first metal connection layers, a first substrate oxide layer having a specific form, and a second connection pattern layer; a process for producing the device; and a microwave plasma treatment apparatus having gas feed ports in a specific position. The highly reliable semiconductor devices can be produced at a high rate at high yields.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，第一金属连接层，具有特定形式的第一衬底氧化物层和第二连接图案层; 一种生产该装置的方法; 以及具有特定位置的气体供给口的微波等离子体处理装置。 高可靠性的半导体器件可以以高产率高产率生产。

公开(公告)号：US20100227474A1

公开(公告)日：2010-09-09

申请号：US12781816

申请日：2010-05-18

申请人： Toshiyuki ARAI ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

发明人： Toshiyuki ARAI ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/7685

摘要： A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

摘要翻译： 例如，制造半导体集成电路器件的方法包括抛光晶片边缘的整个区域，使用抛光滚筒抛光晶片边缘的上表面的三个抛光滚筒，研磨滚筒抛光 晶片边缘的中心部分和抛光滚筒抛光晶片边缘的下表面，从而防止导致晶片边缘上的薄膜脱落的障碍物的出现。

公开(公告)号：US07052995B2

公开(公告)日：2006-05-30

申请号：US10176666

申请日：2002-06-24

申请人： Nobuhito Katsumura ,  Yoshiteru Katsumura ,  Hidemi Sato ,  Norihiro Uchida ,  Fumiyuki Kanai

发明人： Nobuhito Katsumura ,  Yoshiteru Katsumura ,  Hidemi Sato ,  Norihiro Uchida ,  Fumiyuki Kanai

IPC分类号： H01L21/302

CPC分类号： H01L21/7684 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76819

摘要： A buried film and a barrier film are polished together using a slurry in which the polishing rate on a substrate material (in particular, silicon oxide), that on a buried-film material (in particular, tungsten) and that on a barrier-film material (in particular, titanium oxide) are substantially equal to one another. This can materialize a buried structure free from any step or steps, at a high polishing rate.

摘要翻译： 将掩埋膜和阻挡膜使用其中衬底材料（特别是氧化硅）上的抛光速率，掩埋膜材料（特别是钨）上的抛光速率和阻挡膜上的抛光速率 材料（特别是氧化钛）基本上彼此相等。 这可以以高抛光速率实现没有任何步骤或步骤的掩埋结构。

公开(公告)号：US5188975A

公开(公告)日：1993-02-23

申请号：US885852

申请日：1992-05-20

申请人： Masayuki Kojima ,  Shinji Nishihara ,  Fumiyuki Kanai

发明人： Masayuki Kojima ,  Shinji Nishihara ,  Fumiyuki Kanai

IPC分类号： H01L23/522 ,  H01L21/311 ,  H01L21/316 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/768 ,  H01L21/76802 ,  H01L2924/0002

摘要： In a semiconductor integrated circuit device having at least three conductor layers, a connection hole for the lower conductor layer and the upper conductor layer can be formed in self-alignment to the intermediate conductor layer after flattening the underlying insulation film for the upper conductor layer and deterioration of the insulation withstand voltage between the upper conductor layer and the intermediate conductor layer can be prevented.

摘要翻译： 在具有至少三个导体层的半导体集成电路器件中，用于下导体层和上导体层的连接孔可以在使用于上导体层的下面的绝缘膜平坦化之后，与中间导体层自对准地形成，以及 可以防止上导体层和中间导体层之间的绝缘耐受电压的劣化。

公开(公告)号：US07250365B2

公开(公告)日：2007-07-31

申请号：US11167253

申请日：2005-06-28

申请人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

发明人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/7685

摘要： A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

摘要翻译： 例如，制造半导体集成电路器件的方法包括抛光晶片边缘的整个区域，使用抛光滚筒抛光晶片边缘的上表面的三个抛光滚筒，研磨滚筒抛光 晶片边缘的中心部分和抛光滚筒抛光晶片边缘的下表面，从而防止导致晶片边缘上的薄膜脱落的障碍物的出现。

公开(公告)号：US20050250331A1

公开(公告)日：2005-11-10

申请号：US11167253

申请日：2005-06-28

申请人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

发明人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

IPC分类号： H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L21/30 ,  H01L21/302 ,  H01L21/46 ,  H01L21/461

CPC分类号： H01L21/76843 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/7685

摘要： A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

摘要翻译： 例如，制造半导体集成电路器件的方法包括抛光晶片边缘的整个区域，使用抛光滚筒抛光晶片边缘的上表面的三个抛光滚筒，研磨滚筒抛光 晶片边缘的中心部分和抛光滚筒抛光晶片边缘的下表面，从而防止导致晶片边缘上的薄膜脱落的障碍物的出现。

公开(公告)号：US5896150A

公开(公告)日：1999-04-20

申请号：US156909

申请日：1993-11-24

申请人： Atsushi Kobayashi ,  Tatsuo Furuta ,  Fumiyuki Kanai ,  Shinri Sakai ,  Hiroshi Hosokawa

发明人： Atsushi Kobayashi ,  Tatsuo Furuta ,  Fumiyuki Kanai ,  Shinri Sakai ,  Hiroshi Hosokawa

IPC分类号： B41J2/16 ,  B41J2/045 ,  B41J2/04

CPC分类号： B41J2/1629 ,  B41J2/1612 ,  B41J2/1623 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1646 ,  B41J2002/14387 ,  B41J2002/14419

摘要： In an ink-jet type recording head including a nozzle plate provided with nozzle openings, a spacer provided with partitions for partitioning pressure generating chambers, ink supply ports and reservoirs, and a plate member sandwiched and fixed together. Displacement of the plate member is produced by piezoelectric vibrators to thereby generate ink droplets. The spacer is formed by anisotropic etching of a silicon single crystal substrate so that the pressure generating chambers, the ink supply ports and the reservoirs are formed as through-holes communicated with each other. Accordingly, etching conditions for the respective through-holes are made equal to each other. In different embodiments, the spacer includes chamfered portions or a plurality of fine planes and steps along which adhesive spreads during assembly of the head. In a further embodiment, the spacer includes different length partitions are between the pressure generating chambers.

摘要翻译： 在包括具有喷嘴开口的喷嘴板的喷墨型记录头中，设置有用于分隔压力产生室，供墨口和储存器的隔板的间隔件和夹在其中并固定在一起的板构件。 板构件的位移由压电振动器产生，从而产生墨滴。 通过硅单晶基板的各向异性蚀刻形成间隔物，使得压力发生室，供墨口和储存器形成为彼此连通的通孔。 因此，使各个通孔的蚀刻条件相等。 在不同的实施例中，间隔件包括倒角部分或多个精细平面和台阶，在组装头部期间粘合剂沿着该平面和台阶延伸。 在另一个实施例中，间隔件包括在压力产生室之间的不同长度的隔板。

公开(公告)号：US5444012A

公开(公告)日：1995-08-22

申请号：US278073

申请日：1994-07-20

申请人： Keiichi Yoshizumi ,  Kazushi Fukuda ,  Seiichi Ariga ,  Shuji Ikeda ,  Makoto Saeki ,  Kiyoshi Nagai ,  Soichiro Hashiba ,  Shinji Nishihara ,  Fumiyuki Kanai

发明人： Keiichi Yoshizumi ,  Kazushi Fukuda ,  Seiichi Ariga ,  Shuji Ikeda ,  Makoto Saeki ,  Kiyoshi Nagai ,  Soichiro Hashiba ,  Shinji Nishihara ,  Fumiyuki Kanai

IPC分类号： H01L21/66 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8244 ,  H01L23/522 ,  H01L23/525 ,  H01L27/04 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L23/5256 ,  H01L2924/0002 ,  Y10S148/055

摘要： In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.

摘要翻译： 在将构成最终钝化膜的一部分的氧化硅膜沉积到形成在层间绝缘膜上的接合焊盘上的情况下，将氧化硅沉积步骤分成两个阶段，在第一次沉积之后，通过蚀刻将接合焊盘一次曝光 ，然后进行第二沉积，由此形成在层间绝缘膜下面的熔丝元件上形成两级沉积的氧化硅膜，而在焊盘上仅形成沉积在第二层中的氧化硅膜 阶段。 结果，在蚀刻聚酰亚胺树脂，氮化硅膜和氧化硅膜时，连续地露出接合焊盘，在同时形成的孔的底部和熔丝之间保持足够的绝缘膜厚度 元件。 此后，在将探针施加到接合焊盘的同时进行电气测试，并且如果需要，则切割位于孔下方的熔丝元件。

公开(公告)号：US07977234B2

公开(公告)日：2011-07-12

申请号：US12781816

申请日：2010-05-18

申请人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

发明人： Toshiyuki Arai ,  Ryousei Kawai ,  Hirofumi Tsuchiyama ,  Fumiyuki Kanai ,  Shinichi Nakabayashi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/7685

摘要： A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the wafer, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edge of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

摘要翻译： 例如，制造半导体集成电路器件的方法包括抛光晶片边缘的整个区域，使用抛光滚筒抛光晶片边缘的上表面的三个抛光滚筒，研磨滚筒抛光 晶片边缘的中心部分和抛光滚筒抛光晶片边缘的下表面，从而防止导致晶片边缘上的薄膜脱落的障碍物的出现。