公开(公告)号：US20080098253A1

公开(公告)日：2008-04-24

申请号：US12000434

申请日：2007-12-12

申请人： Terry Lee ,  Kevin Ryan ,  Joseph Jeddeloh

发明人： Terry Lee ,  Kevin Ryan ,  Joseph Jeddeloh

IPC分类号： G06F1/08

CPC分类号： G01R31/31937 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254 ,  H03L7/0812 ,  H03L7/0814

摘要： An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

公开(公告)号：US20050204245A1

公开(公告)日：2005-09-15

申请号：US11018384

申请日：2004-12-22

申请人： Terry Lee ,  Kevin Ryan ,  Joseph Jeddeloh

发明人： Terry Lee ,  Kevin Ryan ,  Joseph Jeddeloh

IPC分类号： G01R31/28 ,  G01R31/3193 ,  G06F1/04 ,  G06F11/00 ,  G06F13/00 ,  G06F13/42 ,  G06F19/00 ,  G11C29/50 ,  H04L5/00

CPC分类号： G01R31/31937 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254 ,  H03L7/0812 ,  H03L7/0814

摘要： An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

摘要翻译： 提供了用于逻辑设备的定时校准的改进的技术和相关设备。 校准测试图案首先以比正常操作速度慢的数据速率传输到逻辑设备，以确保在要校准的设备上正确捕获图案。 一旦模式被正确地捕获和存储，测试模式将以正常的操作数据速率传输到逻辑设备，以执行定时校准。 改进的技术和装置允许使用任何位图案作为校准测试图案，由用户编程或使用易于互换的硬件。

公开(公告)号：US20070011392A1

公开(公告)日：2007-01-11

申请号：US11522175

申请日：2006-09-15

申请人： Terry Lee ,  Joseph Jeddeloh

发明人： Terry Lee ,  Joseph Jeddeloh

IPC分类号： G06F12/06

CPC分类号： G06F13/1684 ,  G06F12/0661 ,  G06F13/1694 ,  G06F13/4239

摘要： A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

摘要翻译： 计算机系统包括耦合到多个存储器模块的控制器，每个存储器模块包括存储器集线器和分成多个等级的多个存储器件。 存储器集线器可操作以配置存储器模块以同时寻址任何数量的等级以在高带宽模式，高存储深度模式或这些模式的任何组合中操作。

公开(公告)号：US20070271435A1

公开(公告)日：2007-11-22

申请号：US11881010

申请日：2007-07-24

申请人： Joseph Jeddeloh ,  Terry Lee

发明人： Joseph Jeddeloh ,  Terry Lee

IPC分类号： G06F13/00

CPC分类号： G06F13/1642 ,  G06F13/1673

摘要： A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

摘要翻译： 计算机系统包括耦合到多个存储器模块的存储器集线器控制器。 存储器集线器控制器包括将存储器请求和相应的请求标识符耦合到存储器模块的存储器请求队列。 每个存储器模块基于存储器请求访问存储器件，并且当对应的存储器请求被服务时，从请求标识符产生响应状态信号。 这些响应状态信号与存储器模块耦合到存储器集线器控制器，或者与任何读取数据分离。 存储器集线器控制器使用响应状态信号来控制对存储器模块的存储器请求的耦合，从而控制每个存储器模块中未完成的存储器请求的数量。

公开(公告)号：US20050005181A1

公开(公告)日：2005-01-06

申请号：US10461207

申请日：2003-06-12

申请人： Terry Lee ,  Joseph Jeddeloh

发明人： Terry Lee ,  Joseph Jeddeloh

IPC分类号： G06F20060101 ,  H04L5/00

CPC分类号： H04B10/2504 ,  H04L1/0001 ,  H04L1/242 ,  H04L7/043

摘要： A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

摘要翻译： 一种动态调整通信网络链路控制参数的方法和系统。 通信网络包括通过第一数据链路耦合到接收机的发射机。 发射器和接收器各自具有影响该部件的操作的至少一个相关联的链接控制参数。 根据一种方法，通过第一数据链路传输数据信号，并且捕获发送的数据信号。 将捕获的数据信号的值与这些信号的期望值进行比较，并且调整链路控制参数的值以成功捕获所发送的数字信号。

公开(公告)号：US20060215434A1

公开(公告)日：2006-09-28

申请号：US11311948

申请日：2005-12-19

申请人： Terry Lee ,  Joseph Jeddeloh

发明人： Terry Lee ,  Joseph Jeddeloh

IPC分类号： G11C5/06 ,  G06F12/00

CPC分类号： G11C5/02 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09972 ,  Y02P70/611

摘要： A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

公开(公告)号：US20060212655A1

公开(公告)日：2006-09-21

申请号：US11433201

申请日：2006-05-11

申请人： Joseph Jeddeloh ,  Terry Lee

发明人： Joseph Jeddeloh ,  Terry Lee

IPC分类号： G06F12/00

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4093 ,  G11C11/4096

摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.

摘要翻译： 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括存储写入请求的已发布的写入缓冲器，以便随后发出的读取请求可以首先耦合到存储器件。 写请求地址也被发布在缓冲区中，并与随后的读请求地址进行比较。 在正面比较的情况下，指示读请求被引导到较早写请求所针对的地址，从缓冲器提供读数据。 当存储器件不忙于读取请求时，写入请求可以从发布的写入缓冲区传送到存储器件。 写入请求也可以被累积在发布的写入缓冲器中，直到预定数量的写入请求已经被累积或写入请求已经被发布了预定的持续时间。

公开(公告)号：US20060206738A1

公开(公告)日：2006-09-14

申请号：US11433218

申请日：2006-05-11

申请人： Joseph Jeddeloh ,  Terry Lee

发明人： Joseph Jeddeloh ,  Terry Lee

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/206 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/16 ,  Y02D50/20

摘要： A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by tracking system usage, manifested by read and write commands issued to the memory module, or by measuring temperature changes indicating a level of device activity beyond normal refresh activity. Alternatively, measured activity levels can be transmitted over a system bus to a centralized power management controller which, responsive to the activity level packets transmitted by remote memory modules, direct devices of those remote memory modules to a reduced power state. The centralized power management controller could be disposed on a master memory module or in a memory or system controller.

摘要翻译： 存储器模块包括存储器集线器，该存储器集线器监视存储器模块的利用率，并且当模块未被使用在期望的水平时将存储器模块的设备引导到降低的功率状态。 通过跟踪系统使用情况来监控内存模块的系统利用率，这体现在发给内存模块的读写命令，或通过测量指示超出正常刷新活动的设备活动级别的温度变化。 或者，测量的活动水平可以通过系统总线传送到集中式电力管理控制器，该集中式电力管理控制器响应于由远程存储器模块发送的活动级分组，将那些远程存储器模块的直接设备降低到功率状态。 集中式电源管理控制器可以设置在主存储器模块或存储器或系统控制器中。

公开(公告)号：US20050066137A1

公开(公告)日：2005-03-24

申请号：US10963824

申请日：2004-10-12

申请人： Joseph Jeddeloh ,  Terry Lee

发明人： Joseph Jeddeloh ,  Terry Lee

IPC分类号： G06F13/16 ,  G06F20060101 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G11C5/00

CPC分类号： G06F13/1642 ,  G06F13/1673

摘要： A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

摘要翻译： 计算机系统包括耦合到多个存储器模块的存储器集线器控制器。 存储器集线器控制器包括将存储器请求和对应的请求标识符耦合到存储器模块的存储器请求队列。 每个存储器模块基于存储器请求访问存储器件，并且当对应的存储器请求被服务时，从请求标识符产生响应状态信号。 这些响应状态信号与存储器模块耦合到存储器集线器控制器，或者与任何读取数据分离。 存储器集线器控制器使用响应状态信号来控制对存储器模块的存储器请求的耦合，从而控制每个存储器模块中未完成的存储器请求的数量。

公开(公告)号：US20060288172A1

公开(公告)日：2006-12-21

申请号：US11510150

申请日：2006-08-24

申请人： Terry Lee ,  Joseph Jeddeloh

发明人： Terry Lee ,  Joseph Jeddeloh

IPC分类号： G06F12/00 ,  G06F12/06

CPC分类号： G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6026

摘要： A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.

摘要翻译： 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括历史逻辑，其基于读取存储器请求来预测存储器件中的哪些地址可能随后从其读取数据。 历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。 响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。 标签逻辑存储与预取数据的地址对应的预取地址。 标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。 如果是，则从预取缓冲器读取所请求的数据。 否则，从存储器件读取所请求的数据。