摘要:
A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.
摘要:
A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.
摘要:
A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.
摘要:
A voltage mitigating element mitigating a voltage applied across a gate insulating film in an off state of an insulated gate bipolar transistor (IGBT) is arranged to a gate electrode node of a P-channel MOS transistor provided for suppressing flow-in of holes at the time of turn-off of the IGBT. Withstanding voltage characteristics are improved and an occupation area thereof is reduced while maintaining switching characteristics and a low on-resistance of an insulated gate bipolar transistor.
摘要:
A semiconductor device has a first conductivity-type first semiconductor region, a second conductivity-type second semiconductor region and a second conductivity-type third semiconductor region both located on or above the first semiconductor region, a second conductivity-type fourth semiconductor region between the second semiconductor region and the third semiconductor region, and a first conductivity-type fifth semiconductor region between the third semiconductor region and the fourth semiconductor region. The fourth semiconductor region and the fifth semiconductor region are electrically connected by a conductive member. A distance between the fourth semiconductor region and the third semiconductor region is larger than a width of the fourth semiconductor region.
摘要:
In a semiconductor device and a method of manufacturing the same according to the invention, a p-type diffusion region for electrically connecting a back gate region and an electrode layer together is formed at a source region. Thereby, both of source region and p-type diffusion region are electrically connected to the electrode layer, so that the source region and the back gate region are maintained at the same potential. As a result, it is possible to provide the semiconductor device and the method of manufacturing the same which can suppress operation of a parasitic bipolar transistor formed in the semiconductor device even if a gate electrode has a large width.
摘要:
A resurf structure is provided which includes an n type diffusion region surrounded by a n- diffusion region, in which a part of the joined combination of the n type diffusion region and the n- diffusion region is separated by a narrow p- substrate region in between. An aluminum lead is provided between the separated n- diffusion regions, and a signal is level shifted. A high voltage semiconductor device which includes a small area high voltage isolation region is obtained without process cost increase.
摘要:
A high breakdown voltage pch-MOSFET having a breakdown voltage of 150 V or more and a control element controlling the same are formed in a common n.sup.- epitaxial layer. Only an n-type region of n.sup.- epitaxial layer is distributed at a region located between the high breakdown voltage pch-MOSFET and the control element and extending along the substrate surface. A semiconductor device thus formed achieves a good throughput and reduces a required chip area.
摘要:
A semiconductor device which contains an electrode or an interconnection subjected to a high voltage prevents current leakage due to polarization of a mold resin. In this semiconductor device, a glass coat film 13a covering a semiconductor element has an electrical conductivity in a range defined by the following formula (1) under the conditions of temperature between 17.degree. C. and 145.degree. C.: conductivity.gtoreq.1.times.10.sup.-10 /E . . . (1) (E: an electric field intensity �V/cm!, E.gtoreq.2.times.10.sup.4 �V/cm!) Owing to employment of the electrically conductive glass coat film, an electron current flowing through the conductive glass coat film suppresses an electric field caused by polarization of a mold resin.
摘要:
In a semiconductor device having a low ON resistance, an n.sup.- -type epitaxial layer (1) is formed on an upper surface of an n.sup.+ -type substrate (8) and p-type diffusion regions (2) are selectively formed on its upper surface, while n-type diffusion regions (3) are further formed on upper surfaces thereof. A gate electrode (5) wrapped up in an oxide film (4) is provided on the upper surface of the n.sup.- -type epitaxial layer (1) and above portions of the p-type diffusion regions (2) held between the n.sup.- -type epitaxial layer (1) and the n.sup.+ -type diffusion regions (3). Grooves (9) are formed in the upper surface of the n.sup.- -type epitaxial layer (1) located under a gate electrode (5) to extend perpendicularly to junction planes between the n.sup.- -type epitaxial layer (1) and the p-type diffusion regions (2). While an ON resistance includes an accumulation resistance (Ra) and a JFET resistance (Rj), these resistances can be reduced since a gate width is increased due to formation of the grooves (9) and a current readily flows downwardly along the grooves (9).