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公开(公告)号:US20060151868A1
公开(公告)日:2006-07-13
申请号:US11032666
申请日:2005-01-10
申请人: TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Boris Peres , Alex Ceruzzi
发明人: TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Boris Peres , Alex Ceruzzi
CPC分类号: H01L23/3107 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/49171 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/20755 , H01L2924/2076 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/43 , H01L2924/01006
摘要: A packaged semiconductor device, in particular a gallium nitride semiconductor structure including a lower semiconductor layer and an upper semiconductor layer disposed over a portion of the lower semiconductor layer. The semiconductor structure includes a plurality of mesas projecting upwardly from the lower layer, each of the mesas including a portion of the upper layer and defining an upper contact surface separated form adjacent mesas by a portion of the lower layer surface. The device further includes a die mounting support, wherein the bottom surface of the die is attached to the top surface of the die mounting support; and a plurality of spaced external conductors extending from the support, at least once of said spaced external conductors having a bond wire post at one end thereof; with a bonding wire extending between the bond wire post and a contact region to the top surface of the plurality of mesas.
摘要翻译: 封装的半导体器件,特别是包括下半导体层和设置在下半导体层的一部分上的上半导体层的氮化镓半导体结构。 半导体结构包括从下层向上突出的多个台面,每个台面包括上层的一部分,并且限定由下层表面的一部分与相邻台面分开的上接触表面。 该装置还包括模具安装支撑件,其中模具的底表面附接到模具安装支撑件的顶表面; 以及从所述支撑件延伸的多个间隔开的外部导体,所述间隔开的外部导体中的至少一个在其一端具有接合线柱; 其中接合线在接合线柱和与多个台面的顶表面之间的接触区域之间延伸。
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公开(公告)号:US20050179104A1
公开(公告)日:2005-08-18
申请号:US10780363
申请日:2004-02-17
申请人: Bryan Shelton , Linlin Liu , Alex Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard Stall , Xiang Gao , Ivan Eliashevich
发明人: Bryan Shelton , Linlin Liu , Alex Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard Stall , Xiang Gao , Ivan Eliashevich
IPC分类号: H01L21/60 , H01L29/06 , H01L29/20 , H01L29/47 , H01L29/872 , H01L21/00 , H01L31/0328
CPC分类号: H01L24/81 , H01L29/0692 , H01L29/2003 , H01L29/872 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01023 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/12032 , H01L2924/00
摘要: A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.
摘要翻译: 横向导通肖特基二极管包括形成肖特基接触的多个台面区域,其至少由欧姆接触分开,以减小电流路径长度并减少肖特基接触中的电流拥挤,从而降低器件的正向电阻。 多个台面可以彼此隔离并且具有优化的尺寸和形状以减少前向阻力。 或者,一些台面可以是手指形状并与中央台面或桥台面相交,并且部分或全部欧姆接触件与指状台面相互交错。 指状台面的尺寸和相交结构的周长可以被优化以减小正向阻力。 肖特基二极管可以以倒装芯片布置的方式安装到基座上,这进一步降低了正向电压,并且改善了功率论文并减少了发热。
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公开(公告)号:US20100140627A1
公开(公告)日:2010-06-10
申请号:US12575717
申请日:2009-10-08
申请人: Bryan S. Shelton , Marek K. Pabisz , TingGang Zhu , Linlin Liu , Boris Peres
发明人: Bryan S. Shelton , Marek K. Pabisz , TingGang Zhu , Linlin Liu , Boris Peres
IPC分类号: H01L23/495 , H01L29/20
CPC分类号: H01L23/49562 , H01L21/56 , H01L23/3107 , H01L23/562 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/2919 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/49 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01029 , H01L2924/01031 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/19043 , H01L2924/20755 , H01L2924/2076 , H01L2924/3011 , H01L2924/00014 , H01L2924/0665 , H01L2924/00 , H01L2924/00012
摘要: A packaged semiconductor device including a semiconductor die mounted on a header of a leadframe. A plurality of spaced external conductors extends from the header and at least one of the external conductors has a bond wire post at one end thereof such that a bonding wire extends between the bond wire post and the semiconductor die. The package device also includes a housing, which encloses the semiconductor die, the header, the bonding wire and the bonding wire post resulting in an insulated packaged device.
摘要翻译: 一种封装的半导体器件,包括安装在引线框的头部上的半导体管芯。 多个间隔开的外部导体从集管延伸,并且至少一个外部导体在其一端具有接合线柱,使得接合线在接合线柱和半导体管芯之间延伸。 包装装置还包括壳体,其包围半导体管芯,集管,接合线和接合线柱,形成绝缘的封装装置。
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公开(公告)号:US20060154455A1
公开(公告)日:2006-07-13
申请号:US11371738
申请日:2006-03-09
申请人: Shiping Guo , David Gotthold , Milan Pophristic , Boris Peres , Ivan Eliashevich , Bryan Shelton , Alex Ceruzzi , Michael Murphy , Richard Stall
发明人: Shiping Guo , David Gotthold , Milan Pophristic , Boris Peres , Ivan Eliashevich , Bryan Shelton , Alex Ceruzzi , Michael Murphy , Richard Stall
CPC分类号: H01L29/155 , C30B29/68 , H01L21/02381 , H01L21/02458 , H01L21/02491 , H01L21/02507 , H01L21/0254 , H01L29/2003 , H01L33/007
摘要: A nitride semiconductor is grown on a silicon substrate by depositing a few mono-layers of aluminum to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer from aluminum nitride and a buffer structure including multiple superlattices of AlRGa(1-R)N semiconductors having different compositions and an intermediate layer of GaN or other Ga-rich nitride semiconductor. The resulting structure has superior crystal quality. The silicon substrate used in epitaxial growth is removed before completion of the device so as to provide superior electrical properties in devices such as high-electron mobility transistors.
摘要翻译: 在硅衬底上生长氮化物半导体,通过沉积几个单层铝,以保护硅衬底免受生长过程中使用的氨的影响,然后从氮化铝形成成核层,并形成包含多个超晶格Al 具有不同组成的半导体和GaN或其它富镓氮化物半导体的中间层的半导体。 所得结构具有优异的晶体质量。 在器件完成之前除去用于外延生长的硅衬底,以便在诸如高电子迁移率晶体管的器件中提供优异的电性能。
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公开(公告)号:US08319256B2
公开(公告)日:2012-11-27
申请号:US12821492
申请日:2010-06-23
申请人: Linlin Liu , Milan Pophristic , Boris Peres
发明人: Linlin Liu , Milan Pophristic , Boris Peres
IPC分类号: H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号: H01L29/7786 , H01L29/0657 , H01L29/2003 , H01L29/41758 , H01L29/42316
摘要: A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa. A gate pad is disposed on the first dielectric layer adjacent the mesa. A conductive gate connect strip is located over the gate node and is in contact therewith. The gate strip is in electrical contact with the gate pad. A source via is formed in the first dielectric layer and a source pad is formed in the source via. The conductive source interconnect has a second end in electrical contact with the source pad.
摘要翻译: FET包括衬底,设置在衬底上的缓冲层,设置在缓冲层上的沟道层和设置在沟道层上的阻挡层。 源极,栅极和漏极电极位于阻挡层的上方并沿其纵向方向延伸。 通道和阻挡层的一部分限定沿纵向方向延伸的台面,并且源电极和漏电极延伸超过台面的边缘。 栅电极沿着台面的边缘侧壁延伸。 导电源互连设置在缓冲层之上并且具有电连接到源电极的第一端。 第一介电层设置在缓冲层之上并且在源互连上。 在第一电介质层中形成栅极通孔。 导电栅极节点沿着缓冲层延伸并且电连接沿着台面的侧壁延伸的栅电极的部分。 栅极焊盘设置在与台面相邻的第一电介质层上。 导电栅极连接条位于栅极节点上方并与其接触。 栅极条与栅极焊盘电接触。 源极通孔形成在第一电介质层中,并且在源极通孔中形成源极焊盘。 导电源互连具有与源极焊盘电接触的第二端。
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公开(公告)号:US20110316045A1
公开(公告)日:2011-12-29
申请号:US12821492
申请日:2010-06-23
申请人: Linlin LIU , Milan POPHRISTIC , Boris Peres
发明人: Linlin LIU , Milan POPHRISTIC , Boris Peres
IPC分类号: H01L29/772
CPC分类号: H01L29/7786 , H01L29/0657 , H01L29/2003 , H01L29/41758 , H01L29/42316
摘要: A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa. A gate pad is disposed on the first dielectric layer adjacent the mesa. A conductive gate connect strip is located over the gate node and is in contact therewith. The gate strip is in electrical contact with the gate pad. A source via is formed in the first dielectric layer and a source pad is formed in the source via. The conductive source interconnect has a second end in electrical contact with the source pad.
摘要翻译: FET包括衬底,设置在衬底上的缓冲层,设置在缓冲层上的沟道层和设置在沟道层上的阻挡层。 源极,栅极和漏极电极位于阻挡层的上方并沿其纵向方向延伸。 通道和阻挡层的一部分限定沿纵向方向延伸的台面,并且源电极和漏电极延伸超过台面的边缘。 栅电极沿台面的边缘侧壁延伸。 导电源互连设置在缓冲层之上并且具有电连接到源电极的第一端。 第一介电层设置在缓冲层之上并且在源互连上。 在第一电介质层中形成栅极通孔。 导电栅极节点沿着缓冲层延伸并且电连接沿着台面的侧壁延伸的栅电极的部分。 栅极焊盘设置在与台面相邻的第一电介质层上。 导电栅极连接条位于栅极节点上方并与其接触。 栅极条与栅极焊盘电接触。 源极通孔形成在第一电介质层中,并且在源极通孔中形成源极焊盘。 导电源互连具有与源极焊盘电接触的第二端。
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公开(公告)号:US07084475B2
公开(公告)日:2006-08-01
申请号:US10780363
申请日:2004-02-17
申请人: Bryan S. Shelton , Linlin Liu , Alex D. Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard A. Stall , Xiang Gao , Ivan Eliashevich
发明人: Bryan S. Shelton , Linlin Liu , Alex D. Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard A. Stall , Xiang Gao , Ivan Eliashevich
IPC分类号: H01L29/47
CPC分类号: H01L24/81 , H01L29/0692 , H01L29/2003 , H01L29/872 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01023 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/12032 , H01L2924/00
摘要: A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.
摘要翻译: 横向导通肖特基二极管包括形成肖特基接触的多个台面区域,其至少由欧姆接触分开,以减小电流路径长度并减少肖特基接触中的电流拥挤,从而降低器件的正向电阻。 多个台面可以彼此隔离并且具有优化的尺寸和形状以减少前向阻力。 或者,一些台面可以是手指形状并与中央台面或桥台面相交,并且部分或全部欧姆接触件与指状台面相互交错。 指状台面的尺寸和相交结构的周长可以被优化以减小正向阻力。 肖特基二极管可以以倒装芯片布置的方式安装到基座上,这进一步降低了正向电压,并且改善了功率论文并减少了发热。
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公开(公告)号:US20060145674A1
公开(公告)日:2006-07-06
申请号:US11029266
申请日:2005-01-05
申请人: Bryan Shelton , Boris Peres , Daniel McGlynn
发明人: Bryan Shelton , Boris Peres , Daniel McGlynn
CPC分类号: H02M1/4225 , H02M3/155 , H02M7/2176 , Y02B70/126 , Y02B70/1483
摘要: A converter is provided having an AC input and a DC output. The converter includes a rectifier that receives the AC input and that provides a rectifier output, a series connected current to magnetic field energy storage device and current interrupter connected across the rectifier output and a series connected gallium nitride diode and output charge storage device connected between a midpoint of the series connected magnetic field energy storage device and current interrupter and a terminal of the rectifier output and wherein the converter is characterized in not needing a transient voltage suppression circuit.
摘要翻译: A转换器具有AC输入和DC输出。 该转换器包括一个接收AC输入并提供整流器输出的整流器,连接在整流器输出端的磁场能量存储装置和断流器的串联电流和串联的氮化镓二极管和输出电荷存储装置 串联连接的磁场蓄能装置的中点和电流断流器以及整流器输出的端子,其中转换器的特征在于不需要瞬态电压抑制电路。
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公开(公告)号:US07116567B2
公开(公告)日:2006-10-03
申请号:US11029266
申请日:2005-01-05
申请人: Bryan S. Shelton , Boris Peres , Daniel McGlynn
发明人: Bryan S. Shelton , Boris Peres , Daniel McGlynn
IPC分类号: H02H3/20
CPC分类号: H02M1/4225 , H02M3/155 , H02M7/2176 , Y02B70/126 , Y02B70/1483
摘要: A converter is provided having an AC input and a DC output. The converter includes a rectifier that receives the AC input and that provides a rectifier output, a series connected current to magnetic field energy storage device and current interrupter connected across the rectifier output and a series connected gallium nitride diode and output charge storage device connected between a midpoint of the series connected magnetic field energy storage device and current interrupter and a terminal of the rectifier output and wherein the converter is characterized in not needing a transient voltage suppression circuit.
摘要翻译: A转换器具有AC输入和DC输出。 该转换器包括一个接收AC输入并提供整流器输出的整流器,连接在整流器输出端的磁场能量存储装置和断流器的串联电流和串联的氮化镓二极管和输出电荷存储装置 串联连接的磁场蓄能装置的中点和电流断流器以及整流器输出的端子,其中转换器的特征在于不需要瞬态电压抑制电路。
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公开(公告)号:US07115896B2
公开(公告)日:2006-10-03
申请号:US10721488
申请日:2003-11-25
申请人: Shiping Guo , David Gotthold , Milan Pophristic , Boris Peres , Ivan Eliashevich , Bryan S. Shelton , Alex D. Ceruzzi , Michael Murphy , Richard A. Stall
发明人: Shiping Guo , David Gotthold , Milan Pophristic , Boris Peres , Ivan Eliashevich , Bryan S. Shelton , Alex D. Ceruzzi , Michael Murphy , Richard A. Stall
IPC分类号: H01L29/06
CPC分类号: H01L29/155 , C30B29/68 , H01L21/02381 , H01L21/02458 , H01L21/02491 , H01L21/02507 , H01L21/0254 , H01L29/2003 , H01L33/007
摘要: A nitride semiconductor is grown on a silicon substrate by depositing a few mono-layers of aluminum to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer from aluminum nitride and a buffer structure including multiple superlattices of AlRGa(1-R)N semiconductors having different compositions and an intermediate layer of GaN or other Ga-rich nitride semiconductor. The resulting structure has superior crystal quality. The silicon substrate used in epitaxial growth is removed before completion of the device so as to provide superior electrical properties in devices such as high-electron mobility transistors.
摘要翻译: 在硅衬底上生长氮化物半导体,通过沉积几个单层铝,以保护硅衬底免受生长过程中使用的氨的影响,然后从氮化铝形成成核层,并形成包含多个超晶格Al 具有不同组成的半导体和GaN或其它富镓氮化物半导体的中间层的半导体。 所得结构具有优异的晶体质量。 在器件完成之前除去用于外延生长的硅衬底,以便在诸如高电子迁移率晶体管的器件中提供优异的电性能。
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