Gallium nitride semiconductor device
    1.
    发明申请
    Gallium nitride semiconductor device 失效
    氮化镓半导体器件

    公开(公告)号:US20060145283A1

    公开(公告)日:2006-07-06

    申请号:US11030554

    申请日:2005-01-06

    IPC分类号: H01L27/095 H01L21/338

    摘要: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

    摘要翻译: 由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层,其厚度介于1微米与6微米之间,设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。 优化了层厚度和细长指状物的长度和宽度,以实现具有大于500伏特的击穿电压,超过1安培的电流容量和小于3伏特的正向电压的器件。

    Gallium Nitride Semiconductor Device
    3.
    发明申请
    Gallium Nitride Semiconductor Device 有权
    氮化镓半导体器件

    公开(公告)号:US20090035925A1

    公开(公告)日:2009-02-05

    申请号:US12249099

    申请日:2008-10-10

    IPC分类号: H01L21/425

    摘要: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

    摘要翻译: 由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层,其厚度介于1微米与6微米之间,设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。 优化了层厚度和细长指状物的长度和宽度,以实现具有大于500伏特的击穿电压,超过1安培的电流容量和小于3伏特的正向电压的器件。

    Gallium nitride semiconductor device
    4.
    发明授权
    Gallium nitride semiconductor device 有权
    氮化镓半导体器件

    公开(公告)号:US07863172B2

    公开(公告)日:2011-01-04

    申请号:US12249099

    申请日:2008-10-10

    IPC分类号: H01L29/872 H01L29/47

    摘要: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

    摘要翻译: 由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层,其厚度介于1微米与6微米之间,设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。 优化了层厚度和细长指状物的长度和宽度,以实现具有大于500伏特的击穿电压,超过1安培的电流容量和小于3伏特的正向电压的器件。

    Gallium nitride semiconductor
    5.
    发明申请
    Gallium nitride semiconductor 审中-公开
    氮化镓半导体

    公开(公告)号:US20110101371A1

    公开(公告)日:2011-05-05

    申请号:US12930179

    申请日:2010-12-30

    IPC分类号: H01L29/20

    摘要: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

    摘要翻译: 由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层,其厚度介于1微米与6微米之间,设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。 优化了层厚度和细长指状物的长度和宽度,以实现具有大于500伏特的击穿电压,超过1安培的电流容量和小于3伏特的正向电压的器件。

    Gallium nitride semiconductor device
    6.
    发明授权
    Gallium nitride semiconductor device 失效
    氮化镓半导体器件

    公开(公告)号:US07436039B2

    公开(公告)日:2008-10-14

    申请号:US11030554

    申请日:2005-01-06

    IPC分类号: H01L23/58

    摘要: A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.

    摘要翻译: 由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层,其厚度介于1微米与6微米之间,设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。 优化了层厚度和细长指状物的长度和宽度,以实现具有大于500伏特的击穿电压,超过1安培的电流容量和小于3伏特的正向电压的器件。

    PIN photodiode structure and fabrication process for reducing dielectric delamination
    7.
    发明申请
    PIN photodiode structure and fabrication process for reducing dielectric delamination 有权
    PIN光电二极管结构和减少介电分层的制造工艺

    公开(公告)号:US20060076589A1

    公开(公告)日:2006-04-13

    申请号:US11079708

    申请日:2005-03-14

    IPC分类号: H01L31/113

    CPC分类号: H01L31/02161 H01L31/105

    摘要: A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.

    摘要翻译: PIN光电二极管,以及制造PIN光电二极管的方法,该光电二极管降低了介质分层并提高了器件可靠性。 该工艺通过在衬底上形成第一类型电极层而进行; 形成第一类型电极层的本征层; 在本征层上形成第二类型的电极层; 蚀刻第二类型电极层以限定台面形结构; 以及在所述台面形结构上沉积钝化材料。

    PIN photodiode structure and fabrication process for reducing dielectric delamination
    8.
    发明授权
    PIN photodiode structure and fabrication process for reducing dielectric delamination 有权
    PIN光电二极管结构和减少介电分层的制造工艺

    公开(公告)号:US07439599B2

    公开(公告)日:2008-10-21

    申请号:US11079708

    申请日:2005-03-14

    IPC分类号: H01L31/00

    CPC分类号: H01L31/02161 H01L31/105

    摘要: A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.

    摘要翻译: PIN光电二极管,以及制造PIN光电二极管的方法,该光电二极管减少了介质分层并提高了器件的可靠性 该工艺通过在衬底上形成第一类型电极层而进行; 形成第一类型电极层的本征层; 在本征层上形成第二类型的电极层; 蚀刻第二类型电极层以限定台面形结构; 以及在所述台面形结构上沉积钝化材料。

    Method of making an aligned electrode on a semiconductor structure
    10.
    发明授权
    Method of making an aligned electrode on a semiconductor structure 失效
    在半导体结构上制作排列电极的方法

    公开(公告)号:US06946313B2

    公开(公告)日:2005-09-20

    申请号:US10798770

    申请日:2004-03-12

    申请人: Mark Gottfried

    发明人: Mark Gottfried

    摘要: A method of making an electrode on a semiconductor device including depositing metal on a top surface of a semiconductor structure, and defining a first region of the semiconductor structure for a first electrode by forming a mask over the metal. The mask has an opening so that the first region is covered by the mask and a second region of the structure is aligned with the opening in the mask. Metal aligned with the opening in the mask in the second region is then removed to form a first electrode overlying the first region of the semiconductor structure, and also revealing the top surface of the semiconductor structure in the second region. Material is then removed from the semiconductor structure aligned with opening in the second region to form a second electrode surface for a second electrode.

    摘要翻译: 一种在半导体器件上制造电极的方法,包括在半导体结构的顶表面上沉积金属,并且通过在金属上形成掩模来限定用于第一电极的半导体结构的第一区域。 掩模具有开口,使得第一区域被掩模覆盖,并且结构的第二区域与掩模中的开口对准。 然后去除与第二区域中的掩模中的开口对准的金属,以形成覆盖半导体结构的第一区域的第一电极,并且还露出第二区域中的半导体结构的顶表面。 然后从与第二区域中的开口对准的半导体结构中去除材料,以形成用于第二电极的第二电极表面。