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公开(公告)号：US06653714B2
公开(公告)日：2003-11-25
申请号：US10300440
申请日：2002-11-20
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L29/7317
摘要： A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a base region; a lower portion of the second semiconductor region which at least fills the second opening is formed by lateral growth from a face of the first semiconductor region defining a side wall of the second opening; and the first semiconductor region includes an emitter region and a collector region formed therein.
摘要翻译： 横向双极晶体管包括：衬底; 形成在所述基板上的第一绝缘区域; 选择性地形成在所述第一绝缘区域上的第一导电类型的第一半导体区域; 形成为基本上覆盖所述第一半导体区域的第二绝缘区域; 以及与第一导电类型不同的第二导电类型的第二半导体区域，选择性地形成第二半导体区域，其中：第二绝缘区域具有到达第一半导体区域的表面的第一开口，第一半导体区域 具有到达下面的第一绝缘区域的第二开口，第二开口设置在与第二绝缘区域的第一开口对应的位置; 第二半导体区域形成为填充第一开口和第二开口，从而起基底区域的作用; 至少填充第二开口的第二半导体区域的下部通过从限定第二开口的侧壁的第一半导体区域的表面横向生长形成; 并且第一半导体区域包括形成在其中的发射极区域和集电极区域。
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公开(公告)号：US06503808B1
公开(公告)日：2003-01-07
申请号：US09687251
申请日：2000-10-13
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/7317
摘要： A lateral bipolar transistor includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a bass region; a lower portion of the second semiconductor region which at least fills the second opening is formed by lateral growth from a face of the first semiconductor region defining a side wall of the second opening; and the first semiconductor region includes an emitter region and a collector region formed therein.
摘要翻译： 横向双极晶体管包括：衬底; 形成在所述基板上的第一绝缘区域; 选择性地形成在所述第一绝缘区域上的第一导电类型的第一半导体区域; 形成为基本上覆盖所述第一半导体区域的第二绝缘区域; 以及与第一导电类型不同的第二导电类型的第二半导体区域，选择性地形成第二半导体区域，其中：第二绝缘区域具有到达第一半导体区域的表面的第一开口，第一半导体区域 具有到达下面的第一绝缘区域的第二开口，第二开口设置在与第二绝缘区域的第一开口对应的位置; 第二半导体区域形成为填充第一开口和第二开口，从而起低音区域的作用; 至少填充第二开口的第二半导体区域的下部通过从限定第二开口的侧壁的第一半导体区域的表面横向生长形成; 并且第一半导体区域包括形成在其中的发射极区域和集电极区域。
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公开(公告)号：US06323538B1
公开(公告)日：2001-11-27
申请号：US09480942
申请日：2000-01-11
IPC分类号： H01L27082
CPC分类号： H01L29/66265 , H01L29/7317
摘要： An n-type first single crystal silicon layer is provided as collector region over a silicon substrate with a first insulating film interposed therebetween. A p-type first polysilicon layer is provided as an extension of a base region over the first single crystal silicon layer with a second insulating film interposed therebetween. A p-type second single crystal silicon layer is provided as intrinsic base region on a side of the first single crystal silicon layer, second insulating film and first polysilicon layer. An n-type third single crystal silicon layer is provided as emitter region on a side of the second single crystal silicon layer. And an n-type third polysilicon layer is provided on the first insulating film as extension of an emitter region and is connected to a side of the third single crystal silicon layer.
摘要翻译： 在硅衬底上设置n型第一单晶硅层作为集电极区域，其间插入有第一绝缘膜。 提供p型第一多晶硅层作为第一单晶硅层上的基极区域的延伸，其间插入第二绝缘膜。 在第一单晶硅层，第二绝缘膜和第一多晶硅层的一侧设置p型第二单晶硅层作为本征基极区域。 在第二单晶硅层的一侧设置n型第三单晶硅层作为发射极区域。 并且在第一绝缘膜上设置n型第三多晶硅层作为发射极区域的延伸并且连接到第三单晶硅层的一侧。
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公开(公告)号：US08354693B2
公开(公告)日：2013-01-15
申请号：US12035340
申请日：2008-02-21
申请人： Mitsuyoshi Mori , Toru Okino , Daisuke Ueda , Toshinobu Matsuno
发明人： Mitsuyoshi Mori , Toru Okino , Daisuke Ueda , Toshinobu Matsuno
IPC分类号： H01L31/0336
CPC分类号： H01L27/14689 , H01L27/14632 , H01L27/14645 , H01L27/14687
摘要： A solid state imaging device includes a pixel having a photoelectric conversion element formed on a semiconductor substrate. The photoelectric conversion element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and forming a junction therebetween; a third semiconductor layer formed on the second semiconductor layer and having a smaller band gap energy than the second semiconductor layer, the third semiconductor layer being made of a single-crystal semiconductor and containing an impurity; and a fourth semiconductor layer of the first conductivity type covering a side surface and an upper surface of the third semiconductor layer. Provision of the fourth semiconductor layer can reduce a current flowing in dark conditions.
摘要翻译： 固态成像装置包括具有形成在半导体基板上的光电转换元件的像素。 光电转换元件包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层，形成在第一半导体层上并在其间形成接合部; 形成在所述第二半导体层上并且具有比所述第二半导体层更小的带隙能量的第三半导体层，所述第三半导体层由单晶半导体制成并且含有杂质; 以及覆盖第三半导体层的侧表面和上表面的第一导电类型的第四半导体层。 提供第四半导体层可以减少在黑暗条件下流动的电流。
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公开(公告)号：US20060289894A1
公开(公告)日：2006-12-28
申请号：US11455631
申请日：2006-06-20
申请人： Tomohiro Murata , Yutaka Hirose , Yoshito Ikeda , Tsuyoshi Tanaka , Kaoru Inoue , Daisuke Ueda , Yasuhiro Uemoto
发明人： Tomohiro Murata , Yutaka Hirose , Yoshito Ikeda , Tsuyoshi Tanaka , Kaoru Inoue , Daisuke Ueda , Yasuhiro Uemoto
IPC分类号： H01L31/00
CPC分类号： H01L29/7787 , H01L21/02425 , H01L21/02458 , H01L21/0254 , H01L29/2003 , H01L29/4175 , H01L29/41766
摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1−xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1−N; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.
摘要翻译： 半导体器件具有：形成在导电衬底上并具有高电阻的Al x Ga 1-x N的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，并由未掺杂的GaN和N型Al x Ga 1 -N构成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。 源电极被填充在设置在缓冲层和元件形成层中的通孔中，因此电连接到导电基板。
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公开(公告)号：US20050001235A1
公开(公告)日：2005-01-06
申请号：US10834362
申请日：2004-04-29
申请人： Tomohiro Murata , Yutaka Hirose , Yoshito Ikeda , Tsuyoshi Tanaka , Kaoru Inoue , Daisuke Ueda , Yasuhiro Uemoto
发明人： Tomohiro Murata , Yutaka Hirose , Yoshito Ikeda , Tsuyoshi Tanaka , Kaoru Inoue , Daisuke Ueda , Yasuhiro Uemoto
IPC分类号： H01L21/20 , H01L21/28 , H01L21/338 , H01L29/20 , H01L29/417 , H01L29/778 , H01L29/812 , H01L31/0328 , H01S5/30
CPC分类号： H01L29/7787 , H01L21/02425 , H01L21/02458 , H01L21/0254 , H01L29/2003 , H01L29/4175 , H01L29/41766
摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1-yN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.
摘要翻译： 半导体器件具有：形成在导电基板上并由高电阻的Al x Ga 1-x N构成的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N制成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。 源电极被填充在设置在缓冲层和元件形成层中的通孔中，因此电连接到导电基板。
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公开(公告)号：US07339207B2
公开(公告)日：2008-03-04
申请号：US11455631
申请日：2006-06-20
申请人： Tomohiro Murata , Yutaka Hirose , Yoshito Ikeda , Tsuyoshi Tanaka , Kaoru Inoue , Daisuke Ueda , Yasuhiro Uemoto
发明人： Tomohiro Murata , Yutaka Hirose , Yoshito Ikeda , Tsuyoshi Tanaka , Kaoru Inoue , Daisuke Ueda , Yasuhiro Uemoto
IPC分类号： H01L31/0328
CPC分类号： H01L29/7787 , H01L21/02425 , H01L21/02458 , H01L21/0254 , H01L29/2003 , H01L29/4175 , H01L29/41766
摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1−xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1−N; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.
摘要翻译： 半导体器件具有：形成在导电衬底上并具有高电阻的Al x Ga 1-x N的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N构成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。
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公开(公告)号：US07078743B2
公开(公告)日：2006-07-18
申请号：US10834362
申请日：2004-04-29
申请人： Tomohiro Murata , Yutaka Hirose , Yoshito Ikeda , Tsuyoshi Tanaka , Kaoru Inoue , Daisuke Ueda , Yasuhiro Uemoto
发明人： Tomohiro Murata , Yutaka Hirose , Yoshito Ikeda , Tsuyoshi Tanaka , Kaoru Inoue , Daisuke Ueda , Yasuhiro Uemoto
IPC分类号： H01L31/0328
CPC分类号： H01L29/7787 , H01L21/02425 , H01L21/02458 , H01L21/0254 , H01L29/2003 , H01L29/4175 , H01L29/41766
摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1-yN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.
摘要翻译： 半导体器件具有：形成在导电基板上并具有高电阻的Al x Ga 1-x N的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N制成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。 源电极被填充在设置在缓冲层和元件形成层中的通孔中，因此电连接到导电基板。
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公开(公告)号：US06329262B1
公开(公告)日：2001-12-11
申请号：US09256738
申请日：1999-02-24
IPC分类号： H01L2162
CPC分类号： H01L27/0658 , H01L27/0802
摘要： A semiconductor integrated circuit includes a thermal resistor which is made of a tungsten silicon nitride containing at least about 5% by weight of silicon and formed on a semiconductor substrate directly or via an insulating film. The semiconductor integrated circuit is produced by a method including the steps of: forming a tungsten silicide nitride film on a semiconductor substrate; patterning the tungsten silicide nitride film in a predetermined pattern to form a thermal resistor; and forming a pair of electrodes to be connected to the thermal resistor. The semiconductor integrated circuit is provided so as to have a predetermined resistance by measuring electric characteristics of the semiconductor integrated circuit; obtaining a difference between the measured electric characteristics and desired electric characteristics to calculate a required adjusting amount of a resistance of the thermal resistor; and adjusting the resistance of the thermal resistor by the adjusting amount through heating of the thermal resistor with electric power.
摘要翻译： 半导体集成电路包括由包含至少约5重量％的硅的钨硅氮化物制成的热电阻器，并且直接或经由绝缘膜形成在半导体衬底上。 半导体集成电路通过包括以下步骤的方法制造：在半导体衬底上形成硅化钨化硅膜; 以预定图案图案化硅化钨氮化膜以形成热电阻; 并形成一对要连接到热电阻器的电极。 半导体集成电路通过测量半导体集成电路的电特性而具有预定的电阻; 获得所测量的电特性和所需电特性之间的差以计算热敏电阻的电阻的所需调整量; 并且通过用电力加热热敏电阻器来调整热敏电阻的电阻达到调节量。
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10.发明授权
公开(公告)号：US06025632A
公开(公告)日：2000-02-15
申请号：US988799
申请日：1997-12-11
CPC分类号： H01L27/0658 , H01L27/0802
摘要： A semiconductor integrated circuit includes a thermal resistor which is made of a tungsten silicon nitride containing at least about 5% by weight of silicon and formed on a semiconductor substrate directly or via an insulating film. The semiconductor integrated circuit is produced by a method including the steps of: forming a tungsten silicide nitride film on a semiconductor substrate; patterning the tungsten silicide nitride film in a predetermined pattern to form a thermal resistor; and forming a pair of electrodes to be connected to the thermal resistor. The semiconductor integrated circuit is provided so as to have a predetermined resistance by measuring electric characteristics of the semiconductor integrated circuit; obtaining a difference between the measured electric characteristics and desired electric characteristics to calculate a required adjusting amount of a resistance of the thermal resistor; and adjusting the resistance of the thermal resistor by the adjusting amount through heating of the thermal resistor with electric power.
摘要翻译： 半导体集成电路包括由包含至少约5重量％的硅的钨硅氮化物制成的热电阻器，并且直接或通过绝缘膜形成在半导体衬底上。 半导体集成电路通过包括以下步骤的方法制造：在半导体衬底上形成硅化钨化硅膜; 以预定图案图案化硅化钨氮化膜以形成热电阻; 并形成一对要连接到热电阻器的电极。 半导体集成电路通过测量半导体集成电路的电特性而具有预定的电阻; 获得测量的电特性和期望的电特性之间的差以计算所需热调节电阻的调整量; 并且通过用电力加热热敏电阻器来调整热敏电阻的电阻达到调节量。
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