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    Semiconductor device and method for manufacturing a semiconductor device
    6.
    发明授权
    Semiconductor device and method for manufacturing a semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US07821059B2

    公开(公告)日：2010-10-26

    申请号：US12234197

    申请日：2008-09-19

    申请人： Masao Shingu ,  Shoko Kikuchi ,  Akira Takashima ,  Tsunehiro Ino ,  Koichi Muraoka

    发明人： Masao Shingu ,  Shoko Kikuchi ,  Akira Takashima ,  Tsunehiro Ino ,  Koichi Muraoka

    IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/115

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66833

    摘要： In a semiconductor device, the side walls are made of SiO2, SiN or SiON, and the top insulating film or gate insulating film is made of an oxide including Al, Si, and metal element M so that the number ratio Si/M is set to no less than a number ratio Si/M at a solid solubility limit of SiO2 composition in a composite oxide including metal element M and Al and set to no more than a number ratio Si/M at the condition that the dielectric constant is equal to the dielectric constant of Al2O3 and so that the number ratio Al/M is set to no less than a number ratio Al/M where the crystallization of an oxide of said metal element M is suppressed due to the Al element and set to no more than a number ratio Al/M where the crystallization of the Al2O3 is suppressed due to the metal element M.

    摘要翻译： 在半导体器件中，侧壁由SiO 2，SiN或SiON制成，并且顶部绝缘膜或栅极绝缘膜由包括Al，Si和金属元素M的氧化物制成，使得Si / M的数量比设定 在包含金属元素M和Al的复合氧化物中SiO 2组成的固溶度极限的Si / M的数量比不小于Si / M，在介电常数等于 Al 2 O 3的介电常数和Al / M的数量比被设定为不小于Al / M的数量比，其中所述金属元素M的氧化物的结晶由于Al元素而被抑制，并且设定为不大于 由于金属元素M而抑制了Al 2 O 3的结晶化的数值比Al / M

    Semiconductor device and fabrication method thereof
    8.
    发明申请
    Semiconductor device and fabrication method thereof 失效
    半导体器件及其制造方法

    公开(公告)号：US20080093676A1

    公开(公告)日：2008-04-24

    申请号：US11892940

    申请日：2007-08-28

    申请人： Masao Shingu ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya

    发明人： Masao Shingu ,  Atsuhiro Kinoshita ,  Yoshinori Tsuchiya

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28079 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/1203 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/7851

    摘要： A semiconductor device having a field effect transistor (FET) with enhanced performance by reduction of electrical contact resistance of electrodes and resistance of the electrodes per se is disclosed. The FET includes an n-type FET having a channel region formed in a semiconductor substrate, a gate electrode insulatively overlying the channel region, and a pair of source and drain electrodes which are formed at both ends of the channel region. The source/drain electrodes are made of silicide of a first metal. An interface layer that contains a second metal is formed in the interface between the substrate and the first metal. The second metal is smaller in work function than silicide of the first metal, and the second metal silicide is less in work function than the first metal silicide. A fabrication method of the semiconductor device is also disclosed.

    摘要翻译： 公开了具有通过降低电极的电接触电阻和电极本身的电阻而具有增强的性能的场效应晶体管（FET）的半导体器件。 FET包括具有形成在半导体衬底中的沟道区域，绝缘地覆盖沟道区域的栅极电极和形成在沟道区域两端的一对源极和漏极电极的n型FET。 源极/漏极由第一金属的硅化物制成。 在基板和第一金属之间的界面中形成包含第二金属的界面层。 第二金属的功函数比第一金属的硅化物小，第二金属硅化物的功函数小于第一金属硅化物。 还公开了半导体器件的制造方法。

    Semiconductor device, and method for manufacturing semiconductor device
    9.
    发明授权
    Semiconductor device, and method for manufacturing semiconductor device 失效
    半导体装置及半导体装置的制造方法

    公开(公告)号：US08558301B2

    公开(公告)日：2013-10-15

    申请号：US13208454

    申请日：2011-08-12

    申请人： Masao Shingu ,  Akira Takashima ,  Koichi Muraoka

    发明人： Masao Shingu ,  Akira Takashima ,  Koichi Muraoka

    IPC分类号： H01L29/76

    CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66825

    摘要： There is provided a semiconductor device in which degradation of reliability originating in the interface between an upper insulating layer and an element isolation insulating layer is suppressed. The semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge

    摘要翻译： 提供一种半导体器件，其中抑制源于上绝缘层和元件隔离绝缘层之间的界面的可靠性的劣化。 半导体器件包括：半导体区域; 多个堆叠结构，其各自设置在所述半导体区域上，并且具有依次堆叠的隧道绝缘膜，电荷存储层，上绝缘层和控制电极; 设置在所述多个堆叠结构的侧面上的元件隔离绝缘层; 以及设置在半导体区域和多个堆叠结构中的源极 - 漏极区域。 元件隔离绝缘层包括SiO 2，SiN和SiON中的至少一种，上绝缘层是含有选自稀土金属，Y，Zr和Hf中的至少一种金属M的氧化物，Si ，并且沟道长度方向上的电荷存储层，上绝缘层和控制电极的各自的长度Lcharge，Ltop和Lgate满足关系“Lcharge

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20130234222A1

    公开(公告)日：2013-09-12

    申请号：US13598748

    申请日：2012-08-30

    申请人： Naoki YASUDA ,  Masaaki Higuchi ,  Katsuyuki Sekine ,  Masao Shingu

    发明人： Naoki YASUDA ,  Masaaki Higuchi ,  Katsuyuki Sekine ,  Masao Shingu

    IPC分类号： H01L29/78

    CPC分类号： H01L27/11582 ,  G11C16/0483

    摘要： A semiconductor memory device includes a substrate, a structure body, a semiconductor layer, and a memory film. The memory film is provided between the semiconductor layer and the plurality of electrode films. The memory film includes a charge storage film, a block film, and a tunnel film. The block film is provided between the charge storage film and the plurality of electrode films. The tunnel film is provided between the charge storage film and the semiconductor layer. The tunnel film includes a first film containing silicon oxide, a second film containing silicon oxide, and a third film provided between the first film and the second film and containing silicon oxynitride. When a composition of the silicon oxynitride contained in the third film is expressed by a ratio x of silicon oxide and a ratio (1−x) of silicon nitride, 0.5≦x

    摘要翻译： 半导体存储器件包括衬底，结构体，半导体层和存储膜。 存储膜设置在半导体层和多个电极膜之间。 存储膜包括电荷存储膜，块膜和隧道膜。 阻挡膜设置在电荷存储膜和多个电极膜之间。 隧道膜设置在电荷存储膜和半导体层之间。 隧道膜包括含有氧化硅的第一膜，含有氧化硅的第二膜和设置在第一膜和第二膜之间并含有氮氧化硅的第三膜。 当第三膜中所含的氮氧化硅的组成由氧化硅的比率x和氮化硅的比例（1-x）表示时，0.5×x≤1。