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22 条记录 (耗时 0.033 秒)

    Insulated wire
    1.
    发明授权
    Insulated wire 有权
    绝缘电线

    公开(公告)号：US08586869B2

    公开(公告)日：2013-11-19

    申请号：US13035694

    申请日：2011-02-25

    申请人： Tsuneo Aoi ,  Dai Fujiwara ,  Daisuke Muto ,  Hiromitsu Asai ,  Shinji Kouda ,  Fumiaki Abe

    发明人： Tsuneo Aoi ,  Dai Fujiwara ,  Daisuke Muto ,  Hiromitsu Asai ,  Shinji Kouda ,  Fumiaki Abe

    IPC分类号： H01B7/00

    CPC分类号： C08L81/02 ,  C09D181/02 ,  H01B3/301 ,  H01B3/308 ,  H01B3/427 ,  H02K15/12

    摘要： An inverter surge-resistant insulated wire, having an enamel baked layer, an adhesive layer, and an extrusion-coated resin layer, around the outer periphery of a conductor, wherein the sum of the thickness of the enamel baked layer, the extrusion-coated resin layer, and the adhesive layer is 60 μm or more, wherein the thickness of the enamel baked layer is 50 μm or less, and wherein the extrusion-coated resin layer is formed from a polyphenylene sulfide resin composition, which contains a polyphenylene sulfide polymer having a melt viscosity at 300° C. of 100 Pa·s or more, 2 to 8 mass % of a thermoplastic elastomer, and an antioxidant, and which has a tensile modulus of elasticity at 25° C. of 2,500 MPa or more, and a tensile modulus of elasticity at 250° C. of 10 MPa or more.

    摘要翻译： 在导体的外周附近具有搪瓷烘烤层，粘合剂层和挤出涂覆的树脂层的逆变器耐冲击绝缘线，其中搪瓷烘烤层的厚度，挤出涂覆的 树脂层，粘合剂层为60μm以上，其中搪瓷烘烤层的厚度为50μm以下，其中，所述挤出涂布树脂层由聚苯硫醚树脂组合物形成，所述聚苯硫醚树脂组合物含有聚苯硫醚聚合物 在300℃下的熔体粘度为100Pa·s以上，2〜8质量％的热塑性弹性体和抗氧化剂，其在25℃下的拉伸弹性模量为2500MPa以上， 在250℃下的拉伸弹性模量为10MPa以上。

    Multilayer insulated electric wire and transformer using the same
    2.
    发明授权
    Multilayer insulated electric wire and transformer using the same 有权
    多层绝缘电线和变压器使用相同

    公开(公告)号：US08946557B2

    公开(公告)日：2015-02-03

    申请号：US13409869

    申请日：2012-03-01

    申请人： Hideo Fukuda ,  Yohei Ishii ,  Daisuke Muto ,  Hiroyuki Egawa

    发明人： Hideo Fukuda ,  Yohei Ishii ,  Daisuke Muto ,  Hiroyuki Egawa

    IPC分类号： H01B7/00 ,  H01B3/30 ,  H01B3/42 ,  H01F27/28

    CPC分类号： H01B3/301 ,  H01B3/305 ,  H01B3/423 ,  H01F27/2823

    摘要： A multilayer insulated electric wire having: a conductor; at least three extruded insulating layers covering the conductor; wherein an outermost layer (A) of the insulating layers is composed of an extruded coating layer containing a polyamide resin and the film thickness is 25 μm or less, wherein an inner layer (B) of the extruded insulating layers is composed of an extruded coating layer containing a crystalline resin having a melting point of 225° C. or more or an amorphous resin having a glass transition temperature of 200° C. or more.

    摘要翻译： 一种多层绝缘电线，具有：导体; 覆盖导体的至少三个挤出绝缘层; 其中绝缘层的最外层（A）由包含聚酰胺树脂的挤出涂层组成，膜厚度为25μm以下，其中挤出绝缘层的内层（B）由挤出涂层 含有熔点为225℃以上的结晶性树脂或玻璃化转变温度为200℃以上的无定形树脂。

    EPITAXIAL WAFER MANUFACTURING DEVICE AND MANUFACTURING METHOD
    3.
    发明申请
    EPITAXIAL WAFER MANUFACTURING DEVICE AND MANUFACTURING METHOD 有权
    外延式制造装置和制造方法

    公开(公告)号：US20140230722A1

    公开(公告)日：2014-08-21

    申请号：US14236272

    申请日：2012-08-03

    申请人： Yoshiaki Kageshima ,  Daisuke Muto ,  Kenji Momose

    发明人： Yoshiaki Kageshima ,  Daisuke Muto ,  Kenji Momose

    IPC分类号： C30B25/02 ,  C30B25/10 ,  C30B25/12

    CPC分类号： C30B25/02 ,  C23C16/4401 ,  C30B25/10 ,  C30B25/12 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02529

    摘要： An epitaxial wafer manufacturing device, including a shield (12), which in addition to being removably attached inside a chamber, is arranged in close proximity to the lower surface of a top plate (3). The shield has a substrate (12a) having an opening (13) in the central portion thereof that forces a gas inlet (9) to face the inside of a reaction space (K), and a thin film (12b) that covers the lower surface of the substrate. The surface of the thin film has the shape of surface irregularities corresponding to fine surface irregularities formed in the lower surface of the substrate. When the shield has undergone thermal deformation as a result of being heated by heating means (8), deposits deposited on the lower surface of the shield are inhibited from falling off by the shape of the surface irregularities.

    摘要翻译： 一种外延晶片制造装置，其包括除了可移除地附接在室内之外的屏蔽件（12），其紧邻顶板（3）的下表面布置。 该屏蔽体具有在其中心部分具有开口（13）的基板（12a），其迫使气体入口（9）面向反应空间（K）的内部，并且覆盖下部的薄膜（12b） 基板的表面。 薄膜的表面具有对应于形成在基板的下表面中的细小表面凹凸的表面凹凸的形状。 当屏蔽体被加热装置（8）加热而发生热变形时，由于表面凹凸的形状，沉积在屏蔽层下表面的沉积物被抑制掉。

    CHARGED PARTICLE RADIATION DEVICE AND SOUNDPROOF COVER
    4.
    发明申请
    CHARGED PARTICLE RADIATION DEVICE AND SOUNDPROOF COVER 有权
    充电颗粒辐射装置和防爆罩

    公开(公告)号：US20130082194A1

    公开(公告)日：2013-04-04

    申请号：US13703926

    申请日：2011-06-03

    申请人： Daisuke Muto ,  Masanori Watanabe ,  Hiroshi Tsuji ,  Masaru Matsushima

    发明人： Daisuke Muto ,  Masanori Watanabe ,  Hiroshi Tsuji ,  Masaru Matsushima

    IPC分类号： G10K11/16 ,  G21K5/00

    CPC分类号： G10K11/16 ,  G21K5/00 ,  H01J37/28 ,  H01J2237/0216

    摘要： A charged particle radiation device includes a sample chamber in which a sample stage adapted to mount a sample is installed, a charged particle radiation irradiation section adapted to irradiate the sample with a charged particle radiation to observe and fabricate the sample, sidewalls installed on a periphery of the sample chamber and the charged particle radiation irradiation section, a ceiling board installed on a plane located in an upper part of the sidewalls, and a sound absorbing structure section disposed below the ceiling board, and including a plurality of hole sections and a hollow section communicated with the hole sections. The sound absorbing structure section has an absorption band including a frequency band of a standing wave generated in a space surrounded by the sidewalls and the ceiling board. Further, a soundproof cover may include the sidewalls, ceiling board and sound absorbing structure.

    摘要翻译： 带电粒子辐射装置包括：样品室，其中安装有用于安装样品的样品台;带电粒子辐射照射部分，适于用带电粒子辐射照射样品以观察和制造样品，安装在外围的侧壁 所述样品室和所述带电粒子辐射照射部分，安装在位于所述侧壁的上部的平面上的顶板和设置在所述顶板下方的吸声结构部分，并且包括多个孔部分和中空部 部分与孔部分连通。 吸声结构部分具有吸收带，该吸收带包括在由侧壁和天花板板围住的空间中产生的驻波的频带。 此外，隔音罩可以包括侧壁，天花板和吸音结构。

    INSULATED WIRE
    5.
    发明申请
    INSULATED WIRE 审中-公开
    绝缘线

    公开(公告)号：US20120285724A1

    公开(公告)日：2012-11-15

    申请号：US13556902

    申请日：2012-07-24

    申请人： Makoto OYA ,  Daisuke Muto

    发明人： Makoto OYA ,  Daisuke Muto

    IPC分类号： H01B7/00

    CPC分类号： H01B7/0208 ,  H01B3/306 ,  H01B3/427

    摘要： {Problems} To provide an insulated wire, which is high in a dielectric breakdown resistance even if insulating resin coatings are laminated, because the interlayer adhesiveness is excellent, and which is excellent in a partial discharge resistance, because the dielectric constant is low.{Means to solve} An insulated wire, having directly or indirectly on a conductor (1), at least two laminate units each formed by laminating an insulating layer (21,23) and an insulating layer (22, 24) higher in a dielectric constant than the insulating layer (21, 23), in this order from the conductor side.

    摘要翻译： 为了提供绝缘线，由于层间粘合性优异，由于介电常数低，因此层压粘合性优异，因此绝缘耐击穿性高，即使层压绝缘树脂涂层也具有高的绝缘击穿电阻。 {用于解决}一种直接或间接地在导体（1）上的绝缘线，至少两个层压单元，每个层叠单元通过在电介质中层压绝缘层（21,23）和绝缘层（22,24） 比绝缘层（21,23）恒定，从导体侧开始。

    SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME
    7.
    发明申请
    SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME 有权
    SIC外延波形及其制造方法

    公开(公告)号：US20140175461A1

    公开(公告)日：2014-06-26

    申请号：US14240662

    申请日：2012-09-04

    申请人： Kenji Momose ,  Michiya Odawara ,  Daisuke Muto ,  Yoshiaki Kageshima

    发明人： Kenji Momose ,  Michiya Odawara ,  Daisuke Muto ,  Yoshiaki Kageshima

    IPC分类号： H01L21/02 ,  H01L29/16

    CPC分类号： H01L21/02617 ,  C30B25/186 ,  C30B25/20 ,  C30B29/36 ,  H01L21/02024 ,  H01L21/02046 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/32

    摘要： Provided are a SiC epitaxial wafer in which the surface density of stacking faults is reduced, and a manufacturing method thereof. The method for manufacturing such a SiC epitaxial wafer comprises a step of determining a ratio of basal plane dislocations (BPD), which causes stacking faults in a SiC epitaxial film of a prescribed thickness which is formed on a SiC single crystal substrate having an off angle, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, a step of determining an upper limit of surface density of basal plane dislocations on the growth surface of a SiC single crystal substrate used based on the above ratio, and a step of preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio.

    摘要翻译： 提供了一种其中堆垛层错密度降低的SiC外延晶片及其制造方法。 制造这种SiC外延晶片的方法包括确定基板面位错比（BPD）的步骤，其导致形成在具有偏角的SiC单晶衬底上的规定厚度的SiC外延膜中的堆垛层错 存在于SiC单晶基板的生长面上的基面位错，基于上述比例确定使用的SiC单晶基板的生长面上的基面位错的表面密度的上限的步骤， 以及制备具有等于或小于上述上限的表面密度的SiC单晶衬底的步骤，并且在与所述SiC单晶衬底中使用的外延膜的生长条件相同的条件下，在SiC单晶衬底上形成SiC外延膜 确定比例的步骤。