公开(公告)号：US10223017B2

公开(公告)日：2019-03-05

申请号：US15193126

申请日：2016-06-27

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Chen-Te Chen

IPC: G06F1/32 ,  G06F3/06 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3206

Abstract: A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.

公开(公告)号：US10108366B2

公开(公告)日：2018-10-23

申请号：US15166268

申请日：2016-05-27

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Huei Huang ,  Yi-Lin Lai

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/07 ,  G06F12/1009

Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned a group read-count value. An adjustment of the group read-count values is triggered by a read command of a host. When one read-count value of the group read-count values exceeds a preset range, the controller performs a scan operation to non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the read-count value, so as to check a number of error bits. The controller decides whether to perform a storage block data-moving operation to the non-volatile storage block corresponding to the corresponding logical block address group based on results of the scan operation.

公开(公告)号：US20170285989A1

公开(公告)日：2017-10-05

申请号：US15193126

申请日：2016-06-27

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Chen-Te Chen

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F3/0625 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F3/0634 ,  G06F3/0679 ,  G06F3/0688 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/154 ,  Y02D10/171 ,  Y02D50/20

Abstract: A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.

公开(公告)号：US20170277472A1

公开(公告)日：2017-09-28

申请号：US15166272

申请日：2016-05-27

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Huei Huang ,  Yi-Lin Lai

IPC: G06F3/06 ,  G06F11/07 ,  G06F12/10

CPC classification number: G06F12/1009 ,  G06F3/0616 ,  G06F3/0649 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1048 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7204

Abstract: A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned with a group age parameter. The adjusting of the group age parameters is triggered by a writing instruction of a host. When an age parameter of the group age parameters exceeds a predetermined range, the controller performs a scanning operation to the non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the age parameter, so as to check an error-bit quantity. The controller decides whether the storage block data-moving operation is performed to the non-volatile storage block corresponding to the corresponding logical block address group based on the results of the scanning operation.

公开(公告)号：US09465538B2

公开(公告)日：2016-10-11

申请号：US14469703

申请日：2014-08-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yi-Lin Lai

IPC: G06F12/02 ,  G11C29/42 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F12/06

CPC classification number: G06F3/06 ,  G06F11/1072 ,  G06F12/0246 ,  G06F12/06 ,  G06F2212/7201 ,  G11C29/42 ,  G11C29/52

Abstract: A flash memory control method, storing a logical-to-physical address mapping relationship between a host and a flash memory and a root table in the flash memory and providing a non-volatile storage area storing a root table pointer. A mapping relationship pointer is set forth in the root table to show where the logical-to-physical address mapping relationship is stored in the flash memory. The root table pointer points to the root table stored in the flash memory. In response to a power restoration request issued from the host, the flash memory is accessed based on the root table pointer and thereby the root table is read and the logical-to-physical address mapping relationship is retrieved from the flash memory based on the mapping relationship pointer set forth in the root table.

Abstract translation: 一种闪速存储器控制方法，存储主机与闪速存储器之间的逻辑到物理地址映射关系以及闪速存储器中的根表，并提供存储根表指针的非易失性存储区域。 映射关系指针在根表中列出，以显示逻辑到物理地址映射关系存储在闪存中的位置。 根表指针指向存储在闪存中的根表。 响应从主机发出的电源恢复请求，基于根表指针访问闪存，从而读取根表，并且基于映射从闪存中检索逻辑到物理地址映射关系 关系指针在根表中列出。

公开(公告)号：US11709609B2

公开(公告)日：2023-07-25

申请号：US17195551

申请日：2021-03-08

Applicant: VIA Technologies, Inc.

Inventor： Chin-Yin Tsai ,  Yi-Lin Lai

IPC: G06F3/06 ,  H04L67/1097

CPC classification number: G06F3/0641 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/0689 ,  H04L67/1097

Abstract: A data storage system and a global deduplication method thereof are provided. The data storage system includes multiple storage devices and one dispatch device. The dispatch device divides an original data corresponding to a data writing request into at least one data chunk. The dispatch device performs a summary calculation on one data chunk, so as to generate a representative value. The dispatch device performs a first distribution calculation on the representative value, so as to determine a destination location corresponding to the representative value. The dispatch device transmits the data chunk and the representative value to at least one destination storage device among the storage devices through a communication network according to the destination location. The at least one destination storage device checks the representative value, so as to determine whether to store the data chunk in a storage space of the at least one destination storage device.

公开(公告)号：US10783032B2

公开(公告)日：2020-09-22

申请号：US15662254

申请日：2017-07-27

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Chen-Te Chen ,  Ying-Che Chung

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  H03M13/09 ,  H03M13/15 ,  H03M13/11

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.

公开(公告)号：US10216250B2

公开(公告)日：2019-02-26

申请号：US15193125

申请日：2016-06-27

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Chen-Te Chen

IPC: G06F1/32 ,  G06F12/02 ,  G06F13/14 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3296

Abstract: A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.

公开(公告)号：US09507666B2

公开(公告)日：2016-11-29

申请号：US14561612

申请日：2014-12-05

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yao-Shun Hung ,  Chin-Yin Tsai ,  Yi-Lin Lai

IPC: G06F9/24 ,  G06F15/177 ,  G06F11/14 ,  G06F9/44 ,  G06F11/07

CPC classification number: G06F3/0619 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0673 ,  G06F9/441 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/1076 ,  G06F11/1417

Abstract: A memory chip coupled to a host includes a memory and a controller. Multiple boot images having the same content are pre-loaded in the memory. The controller is coupled to the memory for processing data transmission between the memory chip and the host. The controller further determines whether the memory chip enters a boot mode for the first time. When the memory chip enters the boot mode for the first time, the controller accesses the memory so as to obtain a correct boot image from the boot images and transmits the correct boot image to the host.

Abstract translation: 耦合到主机的存储器芯片包括存储器和控制器。 具有相同内容的多个引导映像被预先加载到存储器中。 控制器耦合到存储器，用于处理存储器芯片和主机之间的数据传输。 控制器进一步确定存储器芯片是否首次进入引导模式。 当存储器芯片第一次进入引导模式时，控制器访问存储器，以从引导映像获得正确的引导映像，并将正确的引导映像传送到主机。

公开(公告)号：US10474529B2

公开(公告)日：2019-11-12

申请号：US15808808

申请日：2017-11-09

Applicant: VIA Technologies, Inc.

Inventor： Ching-Yu Chen ,  Yi-Lin Lai ,  Chen-Te Chen

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/11 ,  G11C29/52

Abstract: An error checking and correcting (ECC) decoding method and apparatus are provided. A decoding circuit decodes a codeword using (or without using) reference information, wherein when the decoding circuit fails to decode a first codeword, the decoding circuit decodes a second codeword to produce decoded data. The decoding circuit checks whether a change has occurred from each codeword bit of the second codeword to a corresponding bit of the decoded data. In accordance with a bit position of the changed corresponding bit, the decoding circuit correspondingly changes the first codeword to a modified codeword, and/or correspondingly changes the reference information to modified information. The decoding circuit performs the ECC decoding again on the modified codeword (or the first codeword) using (or without using) the modified information.