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    Methods for creating electrophoretically insulated vias in semiconductive substrates
    3.
    发明申请
    Methods for creating electrophoretically insulated vias in semiconductive substrates 有权
    在半导体衬底中形成电泳绝缘通孔的方法

    公开(公告)号：US20060063377A1

    公开(公告)日：2006-03-23

    申请号：US11266837

    申请日：2005-11-04

    申请人： Warren Farnworth ,  Dale Collins ,  Steven McDonald

    发明人： Warren Farnworth ,  Dale Collins ,  Steven McDonald

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/316 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

    摘要翻译： 在半导体衬底中形成衬里通孔的方法。 使用电泳沉积技术，衬里材料的胶束沉积在通孔的壁上，与壁的表面反应直到整个壁被衬里材料覆盖。 然后将衬里材料固定在适当位置以形成衬套通孔的层。 然后可以用所需的材料填充衬里的通孔。 例如，衬有绝缘材料的通孔可以填充有诸如铜的材料，以通过基底产生绝缘的导电通孔。

    Methods for creating electrophoretically insulated vias in semiconductive substrates
    4.
    发明申请
    Methods for creating electrophoretically insulated vias in semiconductive substrates 有权
    在半导体衬底中形成电泳绝缘通孔的方法

    公开(公告)号：US20070004197A1

    公开(公告)日：2007-01-04

    申请号：US11516403

    申请日：2006-09-06

    申请人： Warren Farnworth ,  Dale Collins ,  Steven McDonald

    发明人： Warren Farnworth ,  Dale Collins ,  Steven McDonald

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/316 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are deposited on the wall of the via, reacting with the surface of the wall until the entire wall is covered by the lining material. The lining material is then fixed in place to form a layer lining the via. The lined via may then be filled with a desired material. For example, a via lined with an insulative material may be filled with a material such as copper to create an insulated conductive via through the substrate.

    摘要翻译： 提供了用于在半导体衬底中形成衬里通孔的方法。 使用电泳沉积技术，衬里材料的胶束沉积在通孔的壁上，与壁的表面反应直到整个壁被衬里材料覆盖。 然后将衬里材料固定在适当位置以形成衬套通孔的层。 然后可以用所需的材料填充衬里的通孔。 例如，衬有绝缘材料的通孔可以填充有诸如铜的材料，以通过基底产生绝缘的导电通孔。

    Wafer-level testing apparatus
    6.
    发明申请
    Wafer-level testing apparatus 有权
    晶圆级测试仪

    公开(公告)号：US20050146013A1

    公开(公告)日：2005-07-07

    申请号：US11048227

    申请日：2005-02-01

    申请人： Warren Farnworth ,  Steven McDonald

    发明人： Warren Farnworth ,  Steven McDonald

    IPC分类号： G01R31/28 ,  H01L23/58

    CPC分类号： G01R31/2856 ,  G01R31/2831 ,  G01R31/2884 ,  H01L22/32

    摘要： A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with a redistribution circuit that electrically couples at least one die contact to an extended contact such as a bumped contact. A wafer-level redistribution circuit interconnects a plurality of dice and includes a redistribution circuit for coupling between a die contact on one of the dice and a corresponding bumped contact. The wafer-level redistribution circuit further includes a bus conductor traversing each of the plurality of dice for electrically coupling with at least another one of the plurality of dice. At least one other conductor couples the redistribution circuit to the bus conductor.

    摘要翻译： 配置用于晶片级测试的半导体部件包括半导体管芯，其具有电暴露的至少一个管芯接头，用于与再分配电路耦合，该再分配电路将至少一个管芯接触件电耦合到诸如凸起接触件的延伸接触件。 晶片级再分布电路将多个裸片互连，并且包括用于在骰子中的一个上的管芯接触件和相应的凸起接触件之间联接的再分配电路。 晶片级再分配电路还包括一个总线导体，横跨多个芯片中的每一个，用于与多个裸片中的至少另一个芯片电耦合。 至少一个其它导体将再分配电路耦合到总线导体。

    Methods for forming protective layers on semiconductor device substrates
    10.
    发明申请
    Methods for forming protective layers on semiconductor device substrates 失效
    在半导体器件基板上形成保护层的方法

    公开(公告)号：US20050101158A1

    公开(公告)日：2005-05-12

    申请号：US11012569

    申请日：2004-12-15

    申请人： Warren Farnworth ,  Warren Farnworth

    发明人： Warren Farnworth ,  Warren Farnworth

    IPC分类号： H01L23/31 ,  H01L21/44 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/44 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y80/00 ,  H01L23/3157 ,  H01L23/3192 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2224/29099 ,  H01L2924/00

    摘要： Methods for forming protective layers on semiconductor devices, including semiconductor devices that are carried by fabrication substrates, that are parts of assemblies, and that include individual dies, includes at least partially consolidating previously unconsolidated material selectively, in accordance with a program. The method may include use of a machine vision system or other object recognition apparatus to provide precise die-specific alignment. A protective structure may be formed to include at least one layer or segment of dielectric material having a controlled thickness or depth and a precise boundary. The layer or segment may include precisely sized, shaped, and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. Dielectric material may also be employed as a structure to mechanically reinforce a die-to-substrate (e.g., die-to-lead frame) attachment.

    摘要翻译： 在半导体器件上形成保护层的方法，包括由制造衬底承载的半导体器件，其是组件的部件，并且包括单独的裸片，包括根据程序选择性地至少部分地固结先前未合并的材料。 该方法可以包括使用机器视觉系统或其他物体识别装置来提供精确的模具特异性对准。 可以形成保护结构以包括具有受控厚度或深度和精确边界的至少一个介电材料层或段。 层或段可以包括精确尺寸的，成形的和定位的孔，通过该孔可以访问管芯表面上的导电端子，例如接合焊盘。 电介质材料也可以用作结构以机械加强芯片到基板（例如，管芯到引线框架）的连接。