公开(公告)号：US20060254808A1

公开(公告)日：2006-11-16

申请号：US11484962

申请日：2006-07-12

申请人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

发明人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

IPC分类号： H05K1/00

CPC分类号： H05K3/426 ,  H01L21/486 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K2203/072 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/4916 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00

摘要： Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of at least one conductive layer covers a surface of the at least one aperture of the substrate blank. A mask pattern covers a portion of the at least one conductive layer and exposes another portion of the at least one conductive layer to define at least one conductive element, at least a portion of which extends over the surface of the at least one aperture.

摘要翻译： 衬底前体结构包括具有基本上延伸穿过衬底坯料的至少一个孔的衬底坯料。 至少一个导电层的至少一部分覆盖衬底坯料的至少一个孔的表面。 掩模图案覆盖所述至少一个导电层的一部分并且暴露所述至少一个导电层的另一部分以限定至少一个导电元件，其至少一部分在所述至少一个孔的表面上延伸。

公开(公告)号：US20050150683A1

公开(公告)日：2005-07-14

申请号：US10755905

申请日：2004-01-12

申请人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

发明人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

IPC分类号： H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/42 ,  H05K1/03 ,  H05K1/00 ,  H05K1/11

CPC分类号： H05K3/426 ,  H01L21/486 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K2203/072 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/4916 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00

摘要： A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.

摘要翻译： 公开了一种制造衬底的方法。 孔径形成在基板坯件中。 导电层形成在基板的相对表面上以及孔内。 通过掩模和蚀刻在一个或两个相对的表面上限定导电元件。 可以使用附加的导电材料层来提供用于导电元件的阻挡层和贵金属盖。 本发明的方法可用于制造用于封装半导体器件或测试基板的插入器。 还公开了底物前体结构。

公开(公告)号：US20070169343A1

公开(公告)日：2007-07-26

申请号：US11717946

申请日：2007-03-13

申请人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

发明人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

IPC分类号： H05K3/02 ,  H01R9/00

CPC分类号： H05K3/426 ,  H01L21/486 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K2203/072 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/4916 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00

摘要： Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of at least one conductive layer covers a surface of the at least one aperture of the substrate blank. A mask pattern covers a portion of the at least one conductive layer and exposes another portion of the at least one conductive layer to define at least one conductive element, at least a portion of which extends over the surface of the at least one aperture.

摘要翻译： 衬底前体结构包括具有基本上延伸穿过衬底坯料的至少一个孔的衬底坯料。 至少一个导电层的至少一部分覆盖衬底坯料的至少一个孔的表面。 掩模图案覆盖所述至少一个导电层的一部分并且暴露所述至少一个导电层的另一部分以限定至少一个导电元件，其至少一部分在所述至少一个孔的表面上延伸。

公开(公告)号：US20080060193A1

公开(公告)日：2008-03-13

申请号：US11941358

申请日：2007-11-16

申请人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

发明人： Warren Farnworth ,  Steven McDonald ,  Nishant Sinha ,  William Hiatt

IPC分类号： H05K3/06 ,  H05K3/02

CPC分类号： H05K3/426 ,  H01L21/486 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K2203/072 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/4916 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00

摘要： A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.

摘要翻译： 公开了一种制造衬底的方法。 孔径形成在基板坯件中。 导电层形成在基板的相对表面上以及孔内。 通过掩模和蚀刻在一个或两个相对的表面上限定导电元件。 可以使用附加的导电材料层来提供用于导电元件的阻挡层和贵金属盖。 本发明的方法可用于制造用于封装半导体器件或测试基板的插入器。 还公开了底物前体结构。

公开(公告)号：US20070075407A1

公开(公告)日：2007-04-05

申请号：US11608648

申请日：2006-12-08

申请人： Joseph Lindgren ,  Warren Farnworth ,  William Hiatt ,  Nishant Sinha

发明人： Joseph Lindgren ,  Warren Farnworth ,  William Hiatt ,  Nishant Sinha

IPC分类号： H01L23/495

CPC分类号： H01L23/367 ,  H01L23/427 ,  H01L24/31 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/19041 ,  H01L2224/0401

摘要： Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.

摘要翻译： 本文公开了具有改善的散热的微电子器件，制造微电子器件的方法以及冷却微电子器件的方法。 在一个实施例中，微电子器件包括具有第一表面，与第一表面相对的第二表面的微电子衬底以及至少靠近第一表面的多个有源器件。 第二表面具有增加第二表面的表面积的多个传热表面特征。 在另一个实施例中，具有散热器和单相或多相热导体的外壳可以邻近第二表面定位以传递来自有源器件的热量。

公开(公告)号：US20050064695A1

公开(公告)日：2005-03-24

申请号：US10980554

申请日：2004-11-03

申请人： William Hiatt ,  Warren Farnworth ,  Charles Watkins ,  Nishant Sinha

发明人： William Hiatt ,  Warren Farnworth ,  Charles Watkins ,  Nishant Sinha

IPC分类号： H01L21/68 ,  H01L23/31 ,  H01L21/44 ,  G01R31/02

CPC分类号： H01L23/48 ,  B33Y80/00 ,  H01L21/44 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor component includes a die having a pattern of die contacts, and interconnect contacts bonded to the die contacts and encapsulated in an insulating layer. The component also includes terminal contacts formed on tip portions of the interconnect contacts. Alternately the component can include conductors and bonding pads in electrical communication with the interconnect contacts configured to redistribute the pattern of the die contacts. A method for fabricating the component includes the steps of forming the interconnect contacts on the die contacts, and forming the insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming the terminal contacts on the interconnect contacts, or alternately forming the conductors and bonding pads in electrical communication with the interconnect contacts and then forming the terminal contacts on the bonding pads.

摘要翻译： 半导体部件包括具有芯片触点图案的芯片，以及接合到芯片触点并且封装在绝缘层中的互连触点。 该部件还包括形成在互连触点的尖端部分上的端子触头。 或者，该部件可以包括导体和与构造成重新分布芯片触点的图案的互连触点电连通的焊盘。 一种用于制造该部件的方法包括以下步骤：在裸片触点上形成互连触点，并在互连触点上形成绝缘层，同时使尖端部分露出。 该方法还包括在互连触点上形成端子触点的步骤，或者交替地形成与互连触点电连通的导体和焊盘，然后在焊盘上形成端子触点。

公开(公告)号：US20070048998A1

公开(公告)日：2007-03-01

申请号：US11589464

申请日：2006-10-30

申请人： William Hiatt ,  Warren Farnworth ,  Charles Watkins ,  Nishant Sinha

发明人： William Hiatt ,  Warren Farnworth ,  Charles Watkins ,  Nishant Sinha

IPC分类号： H01L21/44

CPC分类号： H01L23/48 ,  B33Y80/00 ,  H01L21/44 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the die, forming a plurality of interconnect contacts on the redistribution contacts, and forming an insulating layer on the interconnect contacts while leaving the tip portions exposed. The method also includes the step of forming terminal contacts on the interconnect contacts, or alternately forming conductors in electrical communication with the interconnect contacts and then forming terminal contacts in electrical communication with the conductors.

摘要翻译： 一种用于制造半导体部件的方法包括以下步骤：提供半导体管芯，在管芯上形成多个再分布接触，在再分布接触上形成多个互连触点，并在互连触点上形成绝缘层，同时留下尖端 暴露部分 该方法还包括在互连触点上形成端子触点的步骤，或者交替地形成与互连触点电连通的导体，然后形成与导体电连通的端子触点。

公开(公告)号：US20050200027A1

公开(公告)日：2005-09-15

申请号：US11052181

申请日：2005-02-07

申请人： Nishant Sinha ,  Warren Farnworth

发明人： Nishant Sinha ,  Warren Farnworth

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H05K3/24 ,  H05K3/42 ,  H01L21/44

CPC分类号： H01L21/486 ,  H01L21/2885 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/244 ,  H05K3/422 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/0394 ,  H01L2924/00

摘要： Methods for fabricating a conductive contact (through-via) through a full thickness of a substrate such as a semiconductor wafer or interposer substrate, and semiconductor devices and systems incorporating the conductive through-via are provided. The conductive contact is fabricated by applying a metal layer onto a backside of a substrate, forming a through-hole through the substrate and the metal layer, sealing the hole in the metal layer by an electroless plating process, and filling the hole by an electroplating or an electroless plating process.

摘要翻译： 提供了通过诸如半导体晶片或插入物基板的基板的整个厚度制造导电接触（贯通孔）的方法，以及结合有导电通孔的半导体器件和系统。 通过在基板的背面上施加金属层，通过基板和金属层形成贯通孔，通过化学镀处理来密封金属层中的孔，并通过电镀填充孔来制造导电接触 或化学镀工艺。

公开(公告)号：US08735902B2

公开(公告)日：2014-05-27

申请号：US12776965

申请日：2010-05-10

申请人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

发明人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

IPC分类号： H01L21/8239

CPC分类号： H01L27/11293 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11563 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

摘要翻译： 记忆及其形成被披露。 一个这样的存储器具有从半导体的第一表面沿第一方向延伸的第一存储单元阵列。 第二阵列的第二存储单元从与半导体的第二表面在第二方向相反的第二方向延伸。 两个阵列可以是非易失性存储器阵列。 例如，存储器阵列之一可以是NAND快闪存储器阵列，而另一个可以是一次可编程存储器阵列。

公开(公告)号：US08707278B2

公开(公告)日：2014-04-22

申请号：US13251463

申请日：2011-10-03

申请人： Gogul Balakrishnan ,  Naoto Maeda ,  Franjo Ivancic ,  Nishant Sinha ,  Aarti Gupta ,  Jing Yang

发明人： Gogul Balakrishnan ,  Naoto Maeda ,  Franjo Ivancic ,  Nishant Sinha ,  Aarti Gupta ,  Jing Yang

IPC分类号： G06F9/45

CPC分类号： G06F8/4434 ,  G06F8/24 ,  G06F8/443 ,  G06F8/51 ,  G06F8/75

摘要： A model is provided for transforming a program with a priori given class hierarchy that is induced by inheritance. An inheritance remover is configured to remove inheritance from a given program to produce an analysis-friendly program which does not include virtual-function pointer tables and runtime libraries associated with inheritance-related operations. The analysis-friendly program preserves the semantics of the given program with respect to a given class hierarchy. A clarifier is configured to identify implicit expressions and function calls and transform the given program into at least one intermediate program having explicit expressions and function calls.

摘要翻译： 提供了一个模型，用于使用由继承引发的先验给定的类层次结构来转换程序。 继承去除器配置为从给定的程序中删除继承，以生成一个不包含与继承相关的操作相关联的虚拟函数指针表和运行时库的分析友好的程序。 分析友好的程序保留给定程序相对于给定类层次结构的语义。 澄清器被配置为识别隐式表达式和函数调用，并将给定程序转换成具有显式表达式和函数调用的至少一个中间程序。