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公开(公告)号：US08115269B2
公开(公告)日：2012-02-14
申请号：US12710072
申请日：2010-02-22
IPC分类号： H01L31/075 , H01L31/105 , H01L31/117
CPC分类号： H01L25/0657 , H01L2224/4824 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.
摘要翻译： 一种制造集成电路封装的技术。 具体地，堆叠的存储器件具有最小的互连。 存储器管芯彼此堆叠并电耦合到衬底。 通孔设置在基板和/或存储器管芯中以便于电连接，而不需要在每个接口之间进行复杂的互连技术。 线键用于完成电路封装。
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公开(公告)号：US20110101514A1
公开(公告)日：2011-05-05
申请号：US13005218
申请日：2011-01-12
IPC分类号： H01L23/34
CPC分类号： H05K3/301 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradeable.
摘要翻译： 一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。 半导体器件的每个接合焊盘都设置在其单个边缘附近。 优选地，半导体器件的至少一部分被暴露。 对准装置附接到载体基板。 可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。 优选地，对准装置将垂直安装的半导体器件封装相对于载体衬底垂直固定。 接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。 垂直安装的半导体器件封装也可以容易地用户升级。
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公开(公告)号：US06979904B2
公开(公告)日：2005-12-27
申请号：US10126067
申请日：2002-04-19
IPC分类号： H01L23/48 , H01L23/52 , H01L25/065 , H01L29/40
CPC分类号： H01L25/0657 , H01L2224/4824 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.
摘要翻译： 一种制造集成电路封装的技术。 具体地，堆叠的存储器件具有最小的互连。 存储器管芯彼此堆叠并电耦合到衬底。 通孔设置在基板和/或存储器管芯中以便于电连接，而不需要在每个接口之间进行复杂的互连技术。 线键用于完成电路封装。
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公开(公告)号：US6087723A
公开(公告)日：2000-07-11
申请号：US50588
申请日：1998-03-30
CPC分类号： H05K3/301 , H01L2924/0002 , Y10T29/4913
摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.
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5.发明授权Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation 有权在不存在离散凸起形成的情况下，能够进行针迹线接合的晶圆凸块的方法公开(公告)号：US07232747B2
公开(公告)日：2007-06-19
申请号：US10928512
申请日：2004-08-26
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L21/288 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05155 , H01L2224/05644 , H01L2224/05655 , H01L2224/45124 , H01L2224/45144 , H01L2224/45164 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/4847 , H01L2224/48644 , H01L2224/48655 , H01L2224/48744 , H01L2224/48755 , H01L2224/78301 , H01L2224/85013 , H01L2224/85205 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01028 , H01L2924/01031 , H01L2924/01032 , H01L2924/01039 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00015 , H01L2924/00012
摘要： A method of bumping a wafer for facilitating bonding of bond wires to elevate the bond location above the passivation layer. The wafer is bumped by disposing the wafer in at least one electroless bath having a nickel-containing solution therein, wherein bumps having a nickel-containing material are formed simultaneously on the exposed bond pads to an elevation sufficient to prevent damage to a passivation layer surrounding the bond pads by contact of a wire bonding capillary. A gold or palladium cap may optionally be formed over the nickel-containing material of the bumps. A method of forming a semiconductor device assembly is also disclosed.
摘要翻译： 一种凸起晶片以促进接合线的接合以提高钝化层上方的结合位置的方法。 通过将晶片设置在其中具有含镍溶液的至少一个无电镀浴中来使晶片凸起，其中具有含镍材料的凸块同时形成在暴露的接合焊盘上至足以防止损坏周围钝化层的高度 通过引线键合毛细管接触的接合垫。 可以可选地在凸块的含镍材料上形成金或钯帽。 还公开了一种形成半导体器件组件的方法。
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公开(公告)号：US07227261B2
公开(公告)日：2007-06-05
申请号：US10648164
申请日：2003-08-26
IPC分类号： H01L23/34
CPC分类号： H05K3/301 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. At least a portion of the semiconductor device may be exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. The alignment device may secure the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.
摘要翻译： 一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。 半导体器件的每个接合焊盘都设置在其单个边缘附近。 可以暴露半导体器件的至少一部分。 对准装置附接到载体基板。 可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。 对准装置可以使垂直安装的半导体器件封装相对于载体衬底垂直地固定。 接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。 垂直安装的半导体器件封装也可以容易地用户升级。
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公开(公告)号：US06228677B1
公开(公告)日：2001-05-08
申请号：US09505214
申请日：2000-02-16
IPC分类号： H01L2144
CPC分类号： H05K3/301 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.
摘要翻译： 一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。 半导体器件的每个接合焊盘都设置在其单个边缘附近。 优选地，半导体器件的至少一部分被暴露。 对准装置附接到载体基板。 可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。 优选地，对准装置将垂直安装的半导体器件封装相对于载体衬底垂直固定。 接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。 垂直安装的半导体器件封装也可以容易地用户升级。
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公开(公告)号：US06215183B1
公开(公告)日：2001-04-10
申请号：US09505493
申请日：2000-02-16
IPC分类号： H01L2334
CPC分类号： H05K3/301 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.
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9.发明授权Method for testing, burning-in, and manufacturing wafer scale integrated circuits and a packaged wafer assembly produced thereby 失效用于测试，烧录和制造晶片级集成电路的方法和由此生产的封装的晶片组件
公开(公告)号：US5440241A
公开(公告)日：1995-08-08
申请号：US847621
申请日：1992-03-06
CPC分类号： G01R31/2863 , G01R1/04 , H01L22/22 , H01L23/32 , H01L2924/0002
摘要： A method for probe testing and burning-in integrated circuits formed within dice or chips on a silicon wafer and then optionally either: (1) dicing the wafer into individual chips for shipment or (2) mating the wafer for shipment with a facing substrate having a temperature coefficient of expansion (TCE) matching the TCE of the wafer. Advantageously, the facing substrate is used for both probe and burn-in operations as well as being made a part of the wafer package in option No. 2 above where either the whole silicon wafer or a partial silicon wafer meeting threshold die requirements is to be shipped. In addition, probe and burn-in operations are carried out rapidly at high yields only after all integrated circuit manufacture has been completed.
摘要翻译： 一种用于探针测试和在硅晶片上形成的骰子或芯片内的燃烧式集成电路的方法，然后可选地：（1）将晶片切割成单独的芯片进行装运，或（2）将晶片与具有正面衬底的对置衬底相配合， 与晶片的TCE匹配的温度膨胀系数（TCE）。 有利地，面对衬底用于探测和老化操作，并且被制成上述选项2中的晶片封装的一部分，其中满足阈值晶片要求的整个硅晶片或部分硅晶片将是 发货。 此外，只有在所有集成电路制造完成后，探头和老化操作才能以高产量快速进行。
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公开(公告)号：US20100148372A1
公开(公告)日：2010-06-17
申请号：US12710072
申请日：2010-02-22
IPC分类号： H01L23/498
CPC分类号： H01L25/0657 , H01L2224/4824 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.
摘要翻译： 一种制造集成电路封装的技术。 具体地，堆叠的存储器件具有最小的互连。 存储器管芯彼此堆叠并电耦合到衬底。 通孔设置在基板和/或存储器管芯中以便于电连接，而不需要在每个接口之间进行复杂的互连技术。 线键用于完成电路封装。
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