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    Multi-standard viterbi processor
    4.
    发明授权
    Multi-standard viterbi processor 有权
    多标准维特比处理器

    公开(公告)号：US08904266B2

    公开(公告)日：2014-12-02

    申请号：US12853589

    申请日：2010-08-10

    申请人： Weihua Tang ,  Nur Engin ,  Frits Anthonie Steenhof ,  Marc Klaassen ,  Andries Pieter Hekstra ,  Sergie Valerjewitsch Sawitzki

    发明人： Weihua Tang ,  Nur Engin ,  Frits Anthonie Steenhof ,  Marc Klaassen ,  Andries Pieter Hekstra ,  Sergie Valerjewitsch Sawitzki

    IPC分类号： H03M13/17 ,  H03M13/00 ,  H03M13/41

    CPC分类号： H03M13/4176 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6519

    摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

    摘要翻译： 各种实施例涉及多标准维特比解码器。 基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。 在给定时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法来处理它们。 各种实施例包括分支度量单位和路径度量单位，其包括可基于可编程值的值而可能或可以不是活动的各种子单元。 各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。 在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

    POWER-REDUCED PRELIMINARY DECODED BITS IN VITERBI DECODERS
    5.
    发明申请
    POWER-REDUCED PRELIMINARY DECODED BITS IN VITERBI DECODERS 有权
    VITERBI解码器中的功率降低的初步解码器

    公开(公告)号：US20110161787A1

    公开(公告)日：2011-06-30

    申请号：US12647885

    申请日：2009-12-28

    申请人： Andries Pieter Hekstra ,  Weihua Tang

    发明人： Andries Pieter Hekstra ,  Weihua Tang

    IPC分类号： H03M13/23 ,  G06F11/10 ,  H04L23/02

    CPC分类号： H03M13/4184

    摘要： Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.

    摘要翻译： 各种实施例涉及维特比解码器中的存储单元和相关方法，用于以功率效率对二进制卷积码进行解码。 用于存储幸存路径的存储单元可以使用寄存器交换方法将从加法比较选择单元接收到的附加信息附加到幸存路径的末端。 示例性方法在幸存路径处理历史中的指定深度之后产生预测路径，并从幸存路径中减去预测路径。 这可能导致构成幸存者路径的大多数位被转换为低能量位，例如逻辑“0”。 在使用寄存器交换方法的差分幸存者路径的随后复制期间，当复制整个幸存者路径时消耗较少的能量，因为幸存路径中的大多数位是逻辑“0”。

    MULTI-STANDARD VITERBI PROCESSOR
    6.
    发明申请
    MULTI-STANDARD VITERBI PROCESSOR 有权
    多标准VITERBI处理器

    公开(公告)号：US20120042229A1

    公开(公告)日：2012-02-16

    申请号：US12853589

    申请日：2010-08-10

    申请人： Weihua Tang ,  Nur Engin ,  Frits Anthonie Steenhof ,  Marc Klaassen ,  Andries Pieter Hekstra ,  Sergei Valerjewitsch Sawitzki

    发明人： Weihua Tang ,  Nur Engin ,  Frits Anthonie Steenhof ,  Marc Klaassen ,  Andries Pieter Hekstra ,  Sergei Valerjewitsch Sawitzki

    IPC分类号： H03M13/03 ,  G06F11/10

    CPC分类号： H03M13/4176 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6519

    摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

    摘要翻译： 各种实施例涉及多标准维特比解码器。 基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。 在给定时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法来处理它们。 各种实施例包括分支度量单位和路径度量单位，其包括可基于可编程值的值而可能或可以不是活动的各种子单元。 各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。 在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

    Power-reduced preliminary decoded bits in viterbi decoders
    8.
    发明授权
    Power-reduced preliminary decoded bits in viterbi decoders 有权
    维特比解码器中功耗降低的初步解码位

    公开(公告)号：US08566683B2

    公开(公告)日：2013-10-22

    申请号：US12647885

    申请日：2009-12-28

    申请人： Andries Pieter Hekstra ,  Weihua Tang

    发明人： Andries Pieter Hekstra ,  Weihua Tang

    IPC分类号： H03M13/03

    CPC分类号： H03M13/4184

    摘要： Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.

    摘要翻译： 各种实施例涉及维特比解码器中的存储单元和相关方法，用于以功率效率对二进制卷积码进行解码。 用于存储幸存路径的存储单元可以使用寄存器交换方法将从加法比较选择单元接收到的附加信息附加到幸存路径的末端。 示例性方法在幸存路径处理历史中的指定深度之后产生预测路径，并从幸存路径中减去预测路径。 这可能导致构成幸存者路径的大多数位被转换为低能量位，例如逻辑“0”。 在使用寄存器交换方法的差分幸存者路径的随后复制期间，当复制整个幸存者路径时消耗较少的能量，因为幸存路径中的大多数位是逻辑“0”。