Method of forming capacitor with a HSG layer
    1.
    发明授权
    Method of forming capacitor with a HSG layer 有权
    用HSG层形成电容器的方法

    公开(公告)号:US06180451B2

    公开(公告)日:2001-01-30

    申请号:US09165143

    申请日:1998-10-01

    IPC分类号: H01L218242

    摘要: A method of forming a DRAM capacitor. A hemispherical grain structure is formed on the surface of the bottom electrode of the capacitor. By employing an additional annealing under a dopant contained ambient, the dopant is diffused into the hemispherical grain structure and distributed at the surface area of the hemispherical grain region.

    摘要翻译: 一种形成DRAM电容器的方法。 在电容器的底部电极的表面上形成半球形晶粒结构。 通过在包含环境的掺杂剂下进行额外的退火,掺杂剂扩散到半球形晶粒结构中并分布在半球形晶粒区域的表面区域。

    Copper damascene technology for ultra large scale integration circuits
    2.
    发明授权
    Copper damascene technology for ultra large scale integration circuits 有权
    铜大马士革技术用于超大规模集成电路

    公开(公告)号:US06174812B1

    公开(公告)日:2001-01-16

    申请号:US09328246

    申请日:1999-06-08

    IPC分类号: H01L2144

    摘要: A copper-palladium alloy damascene technology applied to the ultra large scale integration (ULSI) circuits fabrication is disclosed. First, a TaN barrier is deposited over an oxide layer or in terms of the inter metal dielectric (IMD) layer. Then a copper-palladium seed is deposited over the TaN barrier. Furthermore, a copper-palladium gap-fill electroplating layer is electroplated over the dielectric oxide layer. Second, a copper-palladium annealing process is carried out. Then the copper-palladium electroplating surface is planarized by means of a chemical mechanical polishing (CMP) process. Third, the CoWP cap is self-aligned to the planarized copper-palladium alloy surface. Finally, a second IMD layer is deposited over the first IMD layer. Furthermore, a contact hole in the second dielectric layer over said CoWP cap layer is formed, and then the CoWP cap of the first IMD layer is connected with the copper-palladium alloy bottom surface of the second IMD layer directly. The other deposition processes are subsequently performed the same way.

    摘要翻译: 公开了一种应用于超大规模集成(ULSI)电路制造的铜 - 钯合金镶嵌技术。 首先,在氧化物层上或以金属间电介质(IMD)层方式沉积TaN势垒。 然后将铜钯种子沉积在TaN屏障上。 此外,将铜 - 钯间隙填充电镀层电镀在电介质氧化物层上。 其次,进行铜 - 钯退火处理。 然后通过化学机械抛光(CMP)工艺对铜 - 钯电镀表面进行平面化处理。 第三,CoWP帽与平面化的铜 - 钯合金表面自对准。 最后,第二IMD层沉积在第一IMD层上。 此外,形成在所述CoWP覆盖层上的第二电介质层中的接触孔,然后直接将第一IMD层的CoWP帽与第二IMD层的铜 - 钯合金底面连接。 随后以相同的方式进行其它沉积工艺。

    Method for forming an inter-metal dielectric layer
    4.
    发明授权
    Method for forming an inter-metal dielectric layer 有权
    形成金属间介电层的方法

    公开(公告)号:US06218284B1

    公开(公告)日:2001-04-17

    申请号:US09241841

    申请日:1999-02-01

    IPC分类号: H01L2176

    摘要: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. A fluorinated silicate glass (FSG) layer is formed on the liner layer by using high density plasma chemical vapor deposition (HDPCVD). A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.

    摘要翻译: 描述了一种在没有空隙的情况下形成金属间介电层的方法。 在所提供的基板上形成接线。 每条布线包括其上的保护层。 在衬底上方和衬底上形成衬里层。 通过使用高密度等离子体化学气相沉积(HDPCVD)在衬层上形成氟化硅酸盐玻璃(FSG)层。 FSG层的厚度约为布线厚度的0.9-1倍。 使用HDPCVD在FSG层上形成覆盖层。 盖层的厚度为布线的厚度的约0.2-0.3倍。 在盖层上形成氧化层以达到预定的厚度。 去除介电层的一部分以获得平坦化表面。

    Method of manufacturing multilevel metal interconnect
    5.
    发明授权
    Method of manufacturing multilevel metal interconnect 有权
    制造多层金属互连的方法

    公开(公告)号:US6048796A

    公开(公告)日:2000-04-11

    申请号:US211891

    申请日:1998-12-15

    IPC分类号: H01L21/768 H01L21/00

    CPC分类号: H01L21/7684 H01L21/76829

    摘要: A method is described for manufacturing a multilevel metal interconnects. The method comprises the steps of providing a substrate and then forming a wire on the substrate. A dielectric layer is formed on the substrate and the wire and a protective layer is formed on the dielectric layer. An opening is formed by patterning the protective layer and the dielectric layer and a barrier layer is formed on the protective layer and in the opening. A copper layer is formed on the barrier layer and fills the opening. A portion of the copper layer and the barrier layer are removed by chemical-mechanical polishing.

    摘要翻译: 描述了一种用于制造多层金属互连的方法。 该方法包括以下步骤:提供衬底,然后在衬底上形成线。 在基板和导线上形成电介质层,在电介质层上形成保护层。 通过图案化保护层和电介质层形成开口,并且在保护层和开口中形成阻挡层。 在阻挡层上形成铜层并填充开口。 通过化学机械抛光去除铜层和阻挡层的一部分。

    Method of forming an undoped silicate glass layer on a semiconductor
wafer
    6.
    发明授权
    Method of forming an undoped silicate glass layer on a semiconductor wafer 有权
    在半导体晶片上形成未掺杂的硅酸盐玻璃层的方法

    公开(公告)号:US6001746A

    公开(公告)日:1999-12-14

    申请号:US314928

    申请日:1999-05-20

    IPC分类号: C23C16/40 H01L21/316

    摘要: The present invention provides a method of forming an undoped silicate glass layer on a semiconductor wafer by performing a high density plasma chemical vapor deposition process. The semiconductor wafer being positioned in a deposition chamber. The method comprises forming the undoped silicate glass layer by performing the high density plasma chemical vapor deposition process in the deposition chamber under the following conditions: an argon (Ar) flow rate of 40 to 70 sccm (standard cubic centimeter per minute); an oxygen (O.sub.2) flow rate of 90 to 120 sccm; a silane flow rate of 70 to 100 sccm; a gas pressure of 3 to 10 mtorr; a temperature of 300 to 400.degree. C.; and a low frequency power of 2500 to 3500 watts. Wherein the ratio of Ar to O.sub.2 is 0.53, and O.sub.2 to silane is 1.23.

    摘要翻译: 本发明提供了通过进行高密度等离子体化学气相沉积工艺在半导体晶片上形成未掺杂的硅酸盐玻璃层的方法。 半导体晶片位于沉积室中。 该方法包括通过在以下条件下在沉积室中进行高密度等离子体化学气相沉积工艺来形成未掺杂的硅酸盐玻璃层:氩(Ar)流速为40至70sccm(标准立方厘米每分钟); 氧气(O 2)流量为90至120sccm; 硅烷流量为70〜100sccm; 气体压力为3至10毫托; 温度为300〜400℃。 和2500至3500瓦的低频功率。 其中Ar与O 2的比例为0.53,O 2与硅烷的比例为1.23。

    Optical fiber connector
    7.
    发明授权
    Optical fiber connector 有权
    光纤连接器

    公开(公告)号:US08434949B2

    公开(公告)日:2013-05-07

    申请号:US12892952

    申请日:2010-09-29

    IPC分类号: G02B6/38

    摘要: An optical fiber connector includes a pair of optical fibers and a seat defining a pair of lenses at a front edge thereof and passageways aligned with the lenses respectively and receiving the optical fibers. The seat defines a pair of first apertures at a first surface thereof communicating with the passageways, and a pair of second aperture at a second surface thereof opposite to the first surface communicating with the passageways. Rear insides of the first apertures are aligned with front insides of the second apertures.

    摘要翻译: 光纤连接器包括一对光纤和在其前边缘处限定一对透镜的座,并且分别与透镜对准并接收光纤。 座位在其与通道连通的第一表面处限定一对第一孔,以及在与通道连通的与第一表面相对的第二表面处的一对第二孔。 第一孔的后内侧与第二孔的前内侧对准。

    Burn-in-test socket incorporating with actuating mechanism perfecting leveling of driving plate
    8.
    发明授权
    Burn-in-test socket incorporating with actuating mechanism perfecting leveling of driving plate 失效
    具有致动机构的耐久测试插座,完善驱动板的调平

    公开(公告)号:US08342870B2

    公开(公告)日:2013-01-01

    申请号:US13045546

    申请日:2011-03-11

    IPC分类号: H01R13/62

    CPC分类号: G01R1/0458

    摘要: A socket connector (100) comprises a socket body (5), a plurality of contacts (3) received in the socket body (5), a lid (1) movably mounted on the socket body (5) and moving up and down along a vertical direction, a moving plate (4) movably mounted upon the socket body (5) and moving along a horizontal direction and an operating lever (2) located between the lid (1) and the moving plate (4), the operating lever (2) comprises a press member (22), the press member (22) presses on the top surface of the moving plate (4) to prevent the floating of the moving plate (4) in the vertical direction.

    摘要翻译: 插座连接器(100)包括插座主体(5),容纳在插座主体(5)中的多个触点(3),可移动地安装在插座主体(5)上并沿着 垂直方向,可移动地安装在插座主体(5)上并沿着水平方向移动的移动板(4)和位于盖(1)和移动板(4)之间的操作杆(2) (2)包括按压构件(22),所述按压构件(22)压在所述移动板(4)的顶表面上,以防止所述移动板(4)在垂直方向上浮动。

    Electrical contact for socket connector
    10.
    发明授权
    Electrical contact for socket connector 有权
    插座连接器电接触

    公开(公告)号:US07841864B2

    公开(公告)日:2010-11-30

    申请号:US12538883

    申请日:2009-08-11

    IPC分类号: H01R12/00

    CPC分类号: H01R13/2421

    摘要: An electrical connector (100) includes an insulative housing (2) defining a plurality of passageways (21) and a plurality of contacts (1) received in corresponding passageways. Each contact includes a moveable part (10) forming a pair of guiding beams (105), an immoveable part (20) coupled with the moveable part and a biasing device (30) constantly urging the moveable part away from immoveable part. The immoveable part includes a pair of posts (205) and defines a pair of guiding slots (207). The guiding beams are received in the guiding slots and are capable of moving with regard to the immovable part along opposite surfaces of the immoveable part. The guiding beams and the posts are decussated to surround the biasing device for preventing the biasing device from disengaging therefrom.

    摘要翻译: 电连接器(100)包括限定多个通道(21)的绝缘外壳(2)和容纳在相应通道中的多个触点(1)。 每个触点包括形成一对引导梁(105)的可移动部分(10),与可移动部分联接的不可移动部分(20)和不断地将可移动部分推离远离不可移动部分的偏置装置(30)。 不可移动部分包括一对柱(205)并且限定一对引导槽(207)。 引导梁被容纳在引导槽中并且能够相对于不可移动部分的相对表面相对于不可移动部分移动。 引导梁和柱被折叠以围绕偏置装置,以防止偏置装置与其分离。