公开(公告)号：US09934976B2

公开(公告)日：2018-04-03

申请号：US12317180

申请日：2008-12-18

申请人： Niloy Mukherjee ,  Matt Metz ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S Chau

发明人： Niloy Mukherjee ,  Matt Metz ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert S Chau

IPC分类号： H01L21/285 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/76814

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.

公开(公告)号：US09653548B2

公开(公告)日：2017-05-16

申请号：US15135262

申请日：2016-04-21

申请人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  H01L29/201 ,  H01L29/66 ,  B82Y99/00

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

公开(公告)号：US09337291B2

公开(公告)日：2016-05-10

申请号：US14821561

申请日：2015-08-07

申请人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Van H. Le ,  Seung Hoon Sung ,  Jessica S. Kachian ,  Jack T. Kavalieros ,  Han Wui Then ,  Gilbert Dewey ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/165 ,  H01L29/06 ,  H01L29/205 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78609 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

公开(公告)号：US09236476B2

公开(公告)日：2016-01-12

申请号：US13997972

申请日：2011-12-28

申请人： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

发明人： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L21/84 ,  H01L29/423 ,  H01L27/12 ,  G11C11/412 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L29/785 ,  G11C11/412 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

摘要： Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了用于堆叠存储器件的晶体管的技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的多个翅片结构，其中，多个翅片结构的单个翅片结构包括设置在半导体衬底上的第一隔离层， 第一隔离层，设置在第一沟道层上的第二隔离层和设置在第二隔离层上的第二沟道层，以及与第一沟道层电容耦合以控制通过第一沟道层的电流的栅极端子 用于第一晶体管，并与第二沟道层电容耦合，以控制通过第二沟道层的电流流向第二晶体管。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09123790B2

公开(公告)日：2015-09-01

申请号：US13997897

申请日：2011-12-28

申请人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Van H. Le ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Han Wui Then ,  Marko Radosavljevic

发明人： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Van H. Le ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Han Wui Then ,  Marko Radosavljevic

IPC分类号： H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L23/485 ,  H01L29/66 ,  H01L29/78 ,  B82Y99/00

CPC分类号： H01L29/41791 ,  B82Y40/00 ,  B82Y99/00 ,  G11C7/02 ,  H01L23/485 ,  H01L23/535 ,  H01L27/115 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  H01L2924/0002 ,  Y10S977/762 ,  Y10S977/89 ,  H01L2924/00

摘要： Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

摘要翻译： 本公开的实施例提供了用于减小纳米线晶体管中的寄生电阻的接触技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的隔离层，包括在隔离层上形成的纳米线材料以提供晶体管沟道的沟道层，以及与沟道层耦合的接触点 被配置为在至少一个平面尺寸中围绕所述沟道层的纳米线材料并且为所述晶体管提供源极端子或漏极端子。

公开(公告)号：US09099490B2

公开(公告)日：2015-08-04

申请号：US13631534

申请日：2012-09-28

申请人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L29/08 ,  H01L29/20

CPC分类号： H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

摘要翻译： 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US08987091B2

公开(公告)日：2015-03-24

申请号：US13976840

申请日：2011-12-23

申请人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/336 ,  H01L31/00 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

摘要： III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

摘要翻译： 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和II​​I-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化​​物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

公开(公告)号：US20140203326A1

公开(公告)日：2014-07-24

申请号：US13997607

申请日：2011-12-28

申请人： Niloy Mukherjee ,  Matthew V. Metz ,  james m. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel

发明人： Niloy Mukherjee ,  Matthew V. Metz ,  james m. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel

IPC分类号： H01L29/06 ,  H01L21/02

CPC分类号： H01L29/06 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/0259 ,  H01L21/02617 ,  H01L21/02636 ,  H01L21/02658 ,  H01L21/02664

摘要： Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

摘要翻译： 描述了在非天然表面上形成具有降低的表面粗糙度和体缺陷密度的异质层以及由此形成的器件的方法。 在一个实施例中，该方法包括提供具有晶格常数的顶表面并在衬底的顶表面上沉积第一层的衬底。 第一层具有不同于衬底顶表面的第一晶格常数的晶格常数的顶表面。 第一层被退火和抛光以形成抛光表面。 然后在抛光表面上方沉积第二层。

公开(公告)号：US08785907B2

公开(公告)日：2014-07-22

申请号：US13722746

申请日：2012-12-20

申请人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van H. Le ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Sanaz K. Gardner ,  Sansaptak Dasgupta ,  Willy Rachmady ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Gilbert Dewey ,  Marc C. French ,  Jessica Kachian ,  Satyarth Suri ,  Robert S. Chau

发明人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van H. Le ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Sanaz K. Gardner ,  Sansaptak Dasgupta ,  Willy Rachmady ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Gilbert Dewey ,  Marc C. French ,  Jessica Kachian ,  Satyarth Suri ,  Robert S. Chau

IPC分类号： H01L29/06

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/76232

摘要： An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.

摘要翻译： 实施例包括将材料沉积到衬底上，其中材料包括与衬底（例如Si衬底上的III-V或IV外延（EPI）材料）不同的晶格常数。 一个实施例包括形成在沟槽内的EPI层，其具有随着沟槽向上延伸而变窄的壁。 实施例包括使用多个生长温度在沟槽内形成的EPI层。 当温度变化时，在EPI层中形成的缺陷屏障在沟槽内和缺陷屏障之下包含缺陷。 缺陷屏障之上和沟槽内的EPI层相对无缺陷。 一个实施方案包括在沟槽内退火以引发缺陷湮灭的EPI层。 一个实施例包括形成在沟槽内并覆盖有相对无缺陷的EPI层（仍包含在沟槽中）的EPI超晶格。 本文描述了其它实施例。

公开(公告)号：US20140175379A1

公开(公告)日：2014-06-26

申请号：US13721759

申请日：2012-12-20

申请人： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITIKA GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

发明人： BENJAMIN CHU-KUNG ,  VAN LE ,  ROBERT CHAU ,  SANSAPTAK DASGUPTA ,  GILBERT DEWEY ,  NITIKA GOEL ,  JACK KAVALIEROS ,  MATTHEW METZ ,  NILOY MUKHERJEE ,  RAVI PILLARISETTY ,  WILLY RACHMADY ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  NANCY ZELICK

IPC分类号： H01L29/06

CPC分类号： H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

摘要翻译： 本发明的实施例包括外延层，其以允许该层以两个或三个自由度放松的方式直接接触例如纳米线，翅片或支柱。 外延层可以包括在晶体管的沟道区中。 可以去除纳米线，鳍或柱以提供对外延层的更大的访问。 这样做可以允许围绕外延层的顶部，底部和侧壁的“全向栅极”结构。 本文描述了其它实施例。