公开(公告)号：US06856155B2

公开(公告)日：2005-02-15

申请号：US10266140

申请日：2002-10-07

申请人： Wuu Yean Tay ,  Yong Kian Tan ,  Yong Poo Chia ,  Siu Waf Low ,  Suan Jeung Boon ,  Soon Huat Goh

发明人： Wuu Yean Tay ,  Yong Kian Tan ,  Yong Poo Chia ,  Siu Waf Low ,  Suan Jeung Boon ,  Soon Huat Goh

IPC分类号： G01R31/28 ,  G01R31/02

CPC分类号： G01R31/2863

摘要： A testing scheme for ball-grid array devices of different sizes where the same ball-grid pattern may be tested using the same set of test adapters. A testing scheme includes providing a plurality of devices having a predetermined pattern of solder balls attached, providing a plurality of adapters secured to a test board, each of the adapters including a plurality of test contacts arranged in a pattern corresponding to the predetermined pattern of solder balls, removably attaching the plurality of devices to a device holding apparatus such that the predetermined pattern of solder balls on the devices corresponds to the predetermined pattern of test contacts on the plurality of adapters, then positioning the device holding apparatus to bring the plurality of solder balls in contact with the plurality of test contacts.

摘要翻译： 不同尺寸的球栅阵列器件的测试方案，可以使用相同的一组测试适配器测试相同的球栅图案。 一种测试方案包括提供多个具有附着的焊球预定图案的装置，提供固定在测试板上的多个适配器，每个适配器包括以对应于预定图案焊料的图案布置的多个测试触点 球，可移除地将多个装置附接到装置保持装置，使得装置上的预定图案的焊球对应于多个适配器上的预定图案的试验接触，然后定位装置保持装置以使多个焊料 与多个测试触点接触的球。

公开(公告)号：US20100072603A1

公开(公告)日：2010-03-25

申请号：US12627352

申请日：2009-11-30

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

IPC分类号： H01L23/498

CPC分类号： H01L21/568 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.

摘要翻译： 用于制造具有边缘触点的半导体器件组件和封装的牺牲衬底包括其表面上的导电元件，其被定位成沿着设备衬底上的每个相邻的一对半导体器件之间的街道排列。 半导体器件组件或封装包括半导体器件，半导体器件的有源表面上的再分布层，以及涂覆半导体器件外周的至少部分的电介质材料。 触点的周边部分位于外围边缘，并通过电介质涂层与其隔离。 触点还可以包括在半导体器件的有效表面上部分延伸的上部部分。 组件或封装可以包括任何类型的半导体器件，包括处理器，存储器件和发射极，或光敏器件。

公开(公告)号：US07485562B2

公开(公告)日：2009-02-03

申请号：US11028374

申请日：2005-01-03

申请人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

发明人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

摘要翻译： 本发明定义了在芯片解决方案上提供多芯片多层系统的封装实现。 实现了包含在形成在单独基板中的空腔内的多个和多种已知的良好模具的更大整合。 在多芯片配置之上的附加再分布和互连层可以形成为具有终止于诸如导电凸块或球的电连接的再分布层。 在一个实施例中，衬底空腔以倒装芯片配置接收多个半导体晶片的信号器件连接，例如导电凸块。 然后将衬底的背面的一部分去除足以露出导电凸块的深度。 在另一个实施例中，空腔容纳半导体晶片，其有源表面朝上，其中形成金属层连接并耦合到半导体晶片的接合焊盘或其它电连接器。 还公开了包含包装的计算系统。

公开(公告)号：US07274094B2

公开(公告)日：2007-09-25

申请号：US10233319

申请日：2002-08-28

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

IPC分类号： H01L23/495

CPC分类号： H01L31/0203 ,  H01L2224/16245

摘要： A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.

摘要翻译： 无引线图像传感器封装及其组装方法。 在第一实施例中，图像传感器芯片以倒装芯片方式安装在封装外壳的底侧空腔内，使得图像传感器芯片上的感测电路通过封装壳体的顶侧中的孔露出。 透明的密封剂材料沉积在孔内以包围封装外壳和图像传感器芯片之间的互连结。 透明盖通过密封剂材料保持在孔的适当位置。 图像传感器芯片的背面被暴露。 在特别适用于高端图像传感器的第二实施例中，不需要密封材料。 相反，背盖被密封到封装壳体中的凸缘表面以覆盖底侧空腔。 形成在背盖上的压缩构件与图像传感器芯片接触并保持互连接合完整性。

公开(公告)号：US07579681B2

公开(公告)日：2009-08-25

申请号：US10167284

申请日：2002-06-11

申请人： Yong Poo Chia ,  Suan Jeung Boon ,  Siu Waf Low ,  Yong Loo Neo ,  Bok Leng Ser

发明人： Yong Poo Chia ,  Suan Jeung Boon ,  Siu Waf Low ,  Yong Loo Neo ,  Bok Leng Ser

IPC分类号： H01L23/02 ,  H01L23/52 ,  H01L23/538 ,  H01L23/28 ,  H01L23/31 ,  H01L21/00

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.

摘要翻译： 晶片级封装以及包括晶片级封装中的一个或多个的半导体晶片，电子系统和存储器模块以及在晶片级上制造管芯封装的方法以及包括一个或多个封装的集成电路模块 被提供。 在一个实施例中，管芯封装包括将布置在基板上的两个或多个管芯（通常为半导体晶片）互连的再分配层，再分布层包括连接两个管芯中的每一个的焊盘的第一迹线和连接 两个模具的焊盘焊接到球垫上。 本发明的管芯封装可以包括诸如静态随机存取存储器（SRAM）的存储器件，并且可以作为诸如单列直插存储器模块（SIMM）或双重存储器模块（SIMM）的存储器封装的一部分并入到各种电子系统中 在线内存模块。

公开(公告)号：US07112471B2

公开(公告)日：2006-09-26

申请号：US10693376

申请日：2003-10-23

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L31/0203 ,  H01L2224/16245

摘要： A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.

摘要翻译： 无引线图像传感器封装及其组装方法。 在第一实施例中，图像传感器芯片以倒装芯片方式安装在封装外壳的底侧空腔内，使得图像传感器芯片上的感测电路通过封装壳体的顶侧中的孔露出。 透明的密封剂材料沉积在孔内以包围封装外壳和图像传感器芯片之间的互连结。 透明盖通过密封剂材料保持在孔的适当位置。 图像传感器芯片的背面被暴露。 在特别适用于高端图像传感器的第二实施例中，不需要密封材料。 相反，背盖被密封到封装壳体中的凸缘表面以覆盖底侧空腔。 形成在背盖上的压缩构件与图像传感器芯片接触并保持互连接合完整性。

公开(公告)号：US06825553B2

公开(公告)日：2004-11-30

申请号：US10656352

申请日：2003-09-05

申请人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

发明人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

IPC分类号： H01L2352

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

公开(公告)号：US08698295B2

公开(公告)日：2014-04-15

申请号：US11712270

申请日：2007-02-28

申请人： Yong Poo Chia ,  Suan Jeung Boon ,  Siu Waf Low ,  Yong Loo Neo ,  Bok Leng Ser

发明人： Yong Poo Chia ,  Suan Jeung Boon ,  Siu Waf Low ,  Yong Loo Neo ,  Bok Leng Ser

IPC分类号： H01L23/58 ,  H01L23/02 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level package, and a semiconductor wafer, an electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of memory packages such as single in line memory modules (SIMMs) or dual in line memory modules (DIMMs).

摘要翻译： 包括晶片级封装中的一个或多个的晶片级封装和半导体晶片，电子系统和存储器模块以及在晶片级上制造管芯封装的方法，以及集成电路模块，其包括一个或多个 提供包装。 在一个实施例中，管芯封装包括将布置在基板上的两个或多个管芯（通常为半导体晶片）互连的再分配层，再分布层包括连接两个管芯中的每一个的焊盘的第一迹线和连接 两个模具的焊盘焊接到球垫上。 本发明的管芯封装可以包括诸如静态随机存取存储器（SRAM）的存储器件，并且可以作为诸如单列直插式存储器模块（SIMM）的存储器封装的一部分并入各种电子系统中， 线内存模块（DIMM）。

公开(公告)号：US07368374B2

公开(公告)日：2008-05-06

申请号：US10963346

申请日：2004-10-12

申请人： Yong Poo Chia ,  Suan Jeung Boon ,  Siu Waf Low ,  Yong Loo Neo ,  Bok Leng Ser

发明人： Yong Poo Chia ,  Suan Jeung Boon ,  Siu Waf Low ,  Yong Loo Neo ,  Bok Leng Ser

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/13 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.

摘要翻译： 晶片级封装以及包括晶片级封装中的一个或多个的半导体晶片，电子系统和存储器模块以及在晶片级上制造管芯封装的方法以及包括一个或多个封装的集成电路模块 被提供。 在一个实施例中，管芯封装包括将布置在基板上的两个或多个管芯（通常为半导体晶片）互连的再分布层，再分配层包括连接两个管芯中的每一个的接合焊盘的第一迹线和连接 两个模具的焊盘焊接到球垫上。 本发明的管芯封装可以包括诸如静态随机存取存储器（SRAM）的存储器件，并且可以作为诸如单列直插存储器模块（SIMM）或双重存储器模块（SIMM）的存储器封装的一部分并入到各种电子系统中 在线内存模块。

公开(公告)号：US07208335B2

公开(公告)日：2007-04-24

申请号：US10717421

申请日：2003-11-19

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

IPC分类号： H01L21/00 ,  H01L21/30

CPC分类号： H01L21/568 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A method for fabricating a chip-scale package includes securing a device substrate that carries at least two adjacent semiconductor devices to a sacrificial substrate. The sacrificial substrate may include conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. The device substrate is then severed along each street and the newly formed peripheral edge of each semiconductor device coated with dielectric material. If the sacrificial substrate includes conductive elements, they may be exposed between adjacent semiconductor devices and subsequently serve as lower sections of contacts. Peripheral sections of contacts are formed on the peripheral edge. Upper sections of the contacts may also be formed over the active surfaces of the semiconductor devices. Once the contacts are formed, the sacrificial substrate is substantially removed from the back sides of the semiconductor devices.

摘要翻译： 一种用于制造芯片级封装件的方法包括将承载至少两个相邻半导体器件的器件衬底固定到牺牲衬底。 牺牲衬底可以包括在其表面上的导电元件，其位于沿着设备衬底上每个相邻的一对半导体器件之间的街道对齐。 然后沿着每个街道切割设备基板，并且每个半导体器件的新形成的外围边缘被涂覆有电介质材料。 如果牺牲衬底包括导电元件，则它们可以在相邻的半导体器件之间暴露，并且随后用作接触的下部。 触点的外围部分形成在周边。 触点的上部部分也可以形成在半导体器件的有效表面上。 一旦接触形成，牺牲基底基本上从半导体器件的背面去除。