公开(公告)号：US06856155B2

公开(公告)日：2005-02-15

申请号：US10266140

申请日：2002-10-07

申请人： Wuu Yean Tay ,  Yong Kian Tan ,  Yong Poo Chia ,  Siu Waf Low ,  Suan Jeung Boon ,  Soon Huat Goh

发明人： Wuu Yean Tay ,  Yong Kian Tan ,  Yong Poo Chia ,  Siu Waf Low ,  Suan Jeung Boon ,  Soon Huat Goh

IPC分类号： G01R31/28 ,  G01R31/02

CPC分类号： G01R31/2863

摘要： A testing scheme for ball-grid array devices of different sizes where the same ball-grid pattern may be tested using the same set of test adapters. A testing scheme includes providing a plurality of devices having a predetermined pattern of solder balls attached, providing a plurality of adapters secured to a test board, each of the adapters including a plurality of test contacts arranged in a pattern corresponding to the predetermined pattern of solder balls, removably attaching the plurality of devices to a device holding apparatus such that the predetermined pattern of solder balls on the devices corresponds to the predetermined pattern of test contacts on the plurality of adapters, then positioning the device holding apparatus to bring the plurality of solder balls in contact with the plurality of test contacts.

摘要翻译： 不同尺寸的球栅阵列器件的测试方案，可以使用相同的一组测试适配器测试相同的球栅图案。 一种测试方案包括提供多个具有附着的焊球预定图案的装置，提供固定在测试板上的多个适配器，每个适配器包括以对应于预定图案焊料的图案布置的多个测试触点 球，可移除地将多个装置附接到装置保持装置，使得装置上的预定图案的焊球对应于多个适配器上的预定图案的试验接触，然后定位装置保持装置以使多个焊料 与多个测试触点接触的球。

公开(公告)号：US08525320B2

公开(公告)日：2013-09-03

申请号：US13110060

申请日：2011-05-18

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon ,  Wuu Yean Tay

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon ,  Wuu Yean Tay

IPC分类号： H01L23/02

CPC分类号： H01L23/49527 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/01078

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，一种制造微电子器件的方法包括将具有第一介电壳体的第一管芯封装堆叠在具有第二介电壳体的第二管芯封装的顶部上，使第一壳体的侧表面上的第一金属引线与第二金属 在第二壳体的第二侧表面处引导，并且形成将单独的第一引线连接到单独的第二引线的金属焊料连接器。 在另一个实施例中，制造微电子器件的方法还可以包括通过将金属焊料施加到第一侧表面的一部分，第二侧表面的一部分，以及跨越第一管芯封装和第二侧表面之间的间隙来形成连接器 第二管芯封装，使得连接器由金属焊料形成，其润湿到各个第一引线和各个第二引线。

公开(公告)号：US07190074B2

公开(公告)日：2007-03-13

申请号：US11196584

申请日：2005-08-02

申请人： Yong Kian Tan ,  Wuu Yean Tay

发明人： Yong Kian Tan ,  Wuu Yean Tay

IPC分类号： H01L23/24 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

摘要翻译： 公开了与用于晶片级处理的半导体晶片的重建相关的装置，系统和方法。 将其在其表面中形成的对准空腔的选定的半导体晶片放置成以与基板突出的相似图案中的液体，凝胶或其它可流动的对准液接触，以通过表面张力相互作用来定位骰子。 然后将对准液滴固化以保持定位，并且在骰子和固定装置之间设置底部填充物以加强和维持重建的晶片。 固定板可以与底部填充物组合使用，以增加额外的强度并简化处理。 重构的晶片可以经受晶片级处理，晶片级测试和老化使用重建的晶片特别方便。 由牺牲材料组成的对准液可以从重建的晶片中去除，并且所产生的空隙填充以形成所得骰子上的互连或接触。

公开(公告)号：US20080311685A1

公开(公告)日：2008-12-18

申请号：US12200027

申请日：2008-08-28

申请人： Yong Kian Tan ,  Wuu Yean Tay

发明人： Yong Kian Tan ,  Wuu Yean Tay

IPC分类号： H01L21/70

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

摘要翻译： 公开了关于用于晶片级处理的半导体晶片的重建的方法。 将其在其表面中形成的对准空腔的选定的半导体晶片放置成以与基板突出的相似图案中的液体，凝胶或其它可流动的对准液接触，以通过表面张力相互作用来定位骰子。 然后将对准液滴固化以保持定位，并且在骰子和固定装置之间设置底部填充物以加强和维持重建的晶片。 固定板可以与底部填充物组合使用，以增加额外的强度并简化处理。 重构的晶片可以经受晶片级处理，晶片级测试和老化使用重建的晶片特别方便。 由牺牲材料组成的对准液可以从重建的晶片中去除，并且所产生的空隙填充以形成所得骰子上的互连或接触。

公开(公告)号：US07820459B2

公开(公告)日：2010-10-26

申请号：US12200027

申请日：2008-08-28

申请人： Yong Kian Tan ,  Wuu Yean Tay

发明人： Yong Kian Tan ,  Wuu Yean Tay

IPC分类号： H01L21/66 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/46

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

摘要翻译： 公开了关于用于晶片级处理的半导体晶片的重建的方法。 将其在其表面中形成的对准空腔的选定的半导体晶片放置成以与基板突出的相似图案中的液体，凝胶或其它可流动的对准液接触，以通过表面张力相互作用来定位骰子。 然后将对准液滴固化以保持定位，并且在骰子和固定装置之间设置底部填充物以加强和维持重建的晶片。 固定板可以与底部填充物组合使用，以增加额外的强度并简化处理。 重构的晶片可以经受晶片级处理，晶片级测试和老化使用重建的晶片特别方便。 由牺牲材料组成的对准液可以从重建的晶片中去除，并且所产生的空隙填充以形成所得骰子上的互连或接触。

公开(公告)号：US07573006B2

公开(公告)日：2009-08-11

申请号：US11196757

申请日：2005-08-02

申请人： Yong Kian Tan ,  Wuu Yean Tay

发明人： Yong Kian Tan ,  Wuu Yean Tay

IPC分类号： B23K10/00

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

摘要翻译： 公开了与用于晶片级处理的半导体晶片的重建有关的装置，系统和方法。 将其在其表面中形成的对准空腔的选定的半导体晶片放置成以与基板突出的相似图案中的液体，凝胶或其它可流动的对准液接触，以通过表面张力相互作用来定位骰子。 然后将对准液滴固化以保持定位，并且在骰子和固定装置之间设置底部填充物以加强和维持重建的晶片。 固定板可以与底部填充物组合使用，以增加额外的强度并简化处理。 重构的晶片可以经受晶片级处理，晶片级测试和老化使用重建的晶片特别方便。 由牺牲材料组成的对准液可以从重建的晶片中去除，并且所产生的空隙填充以形成所得骰子上的互连或接触。

公开(公告)号：US07425462B2

公开(公告)日：2008-09-16

申请号：US11449472

申请日：2006-06-07

申请人： Yong Kian Tan ,  Wuu Yean Tay

发明人： Yong Kian Tan ,  Wuu Yean Tay

IPC分类号： H01L21/44

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

摘要翻译： 公开了关于用于晶片级处理的半导体晶片的重建的方法。 将其在其表面中形成的对准空腔的选定的半导体晶片放置成以与基板突出的相似图案中的液体，凝胶或其它可流动的对准液接触，以通过表面张力相互作用来定位骰子。 然后将对准液滴固化以保持定位，并且在骰子和固定装置之间设置底部填充物以加强和维持重建的晶片。 固定板可以与底部填充物组合使用，以增加额外的强度并简化处理。 重构的晶片可以经受晶片级处理，晶片级测试和老化使用重建的晶片特别方便。 由牺牲材料组成的对准液可以从重建的晶片中去除，并且所产生的空隙填充以形成所得骰子上的互连或接触。

公开(公告)号：US07071012B2

公开(公告)日：2006-07-04

申请号：US10645389

申请日：2003-08-21

申请人： Yong Kian Tan ,  Wuu Yean Tay

发明人： Yong Kian Tan ,  Wuu Yean Tay

IPC分类号： H01L21/66 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/46

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

公开(公告)号：US07915718B2

公开(公告)日：2011-03-29

申请号：US10150892

申请日：2002-05-17

申请人： Teck Kheng Lee ,  Wuu Yean Tay ,  Kian Chai Lee

发明人： Teck Kheng Lee ,  Wuu Yean Tay ,  Kian Chai Lee

IPC分类号： H01L23/495 ,  H01L29/40

CPC分类号： H01L23/5383 ,  H01L21/563 ,  H01L23/13 ,  H01L23/50 ,  H01L23/5387 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/00

摘要： A method and apparatus for increasing the integrated circuit density in a flip-chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second surface thereof, wherein the recesses are arranged in a plurality of recess patterns. The interposer substrate also provides enhanced accessibility for test probes for electrical testing of the resulting flip-chip semiconductor device assembly.

摘要翻译： 一种用于增加倒装芯片半导体器件组件中的集成电路密度的方法和装置，其包括便于与各种半导体管芯导电凸块布置使用的插入器衬底。 插入器基板包括形成在其第一表面和第二表面中的至少一个中的多个凹部，其中凹部被布置成多个凹部图案。 插入器基板还为所得到的倒装芯片半导体器件组件的电测试提供用于测试探针的增强的可访问性。

公开(公告)号：US07754531B2

公开(公告)日：2010-07-13

申请号：US11600665

申请日：2006-11-15

申请人： Wuu Yean Tay ,  Cher Khng Victor Tan

发明人： Wuu Yean Tay ,  Cher Khng Victor Tan

IPC分类号： H01L21/48 ,  H01L23/48 ,  H01L43/00

CPC分类号： H01L24/96 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  Y10T29/49222 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2224/05147 ,  H01L2224/05166

摘要： Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality of vias through the dielectric layer between the dies, and fabricating a plurality of conductive links in corresponding vias. In another embodiment, a plurality of microelectronic devices includes a support member, a plurality of microelectronic dies coupled to the support member, a dielectric layer over the dies and at least a portion of the support member, and a plurality of conductive links extending from a first surface of the dielectric layer to a second surface. The dies include an integrated circuit and a plurality of bond-pads coupled to the integrated circuit, and the conductive links are disposed between the dies.

摘要翻译： 本文公开了用于封装通过这些方法形成的微电子器件和微电子器件的方法。 在一个实施例中，一种方法包括将多个微电子管芯耦合到支撑构件，用介电层覆盖模具和支撑构件的至少一部分，形成通过模具之间的介电层的多个通孔，并且制造 相应通孔中的多个导电连接。 在另一个实施例中，多个微电子器件包括支撑构件，耦合到支撑构件的多个微电子模具，在模具和支撑构件的至少一部分上的电介质层，以及从一个 介电层的第一表面到第二表面。 模具包括集成电路和耦合到集成电路的多个接合焊盘，并且导电连接件设置在管芯之间。