公开(公告)号：US20130256760A1

公开(公告)日：2013-10-03

申请号：US13436644

申请日：2012-03-30

申请人： Xinyu Bao ,  Errol Antonio C. Sanchez ,  David K. Carlson ,  Zhiyuan Ye

发明人： Xinyu Bao ,  Errol Antonio C. Sanchez ,  David K. Carlson ,  Zhiyuan Ye

IPC分类号： H01L29/267 ,  H01L21/20

CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02694 ,  H01L29/267 ,  Y10T117/1008

摘要： A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

摘要翻译： 一种在硅衬底上形成保形III / V层的方法，其上形成有III / V层的所得衬底。 该方法包括从衬底去除原生氧化物，将衬底定位在处理室内，将衬底加热至第一温度，将衬底冷却至第二温度，将III族前体流入处理室，保持第二温度，同时 将III族前体和V族前体流入处理室，直到形成共形层，同时停止III族前体的流动，将处理室加热至退火温度，并将处理室冷却至第二温度。 可以通过使用优先蚀刻电介质区域的卤化物气蚀刻来选择性地制备III / V层的沉积。

公开(公告)号：US08603898B2

公开(公告)日：2013-12-10

申请号：US13436644

申请日：2012-03-30

申请人： Xinyu Bao ,  Errol Antonio C. Sanchez ,  David K. Carlson ,  Zhiyuan Ye

发明人： Xinyu Bao ,  Errol Antonio C. Sanchez ,  David K. Carlson ,  Zhiyuan Ye

IPC分类号： H01L21/20 ,  H01L21/36 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14 ,  C30B11/00 ,  C30B35/00

CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02694 ,  H01L29/267 ,  Y10T117/1008

摘要： A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

摘要翻译： 一种在硅衬底上形成保形III / V层的方法，其上形成有III / V层的所得衬底。 该方法包括从衬底去除原生氧化物，将衬底定位在处理室内，将衬底加热至第一温度，将衬底冷却至第二温度，将III族前体流入处理室，保持第二温度，同时 将III族前体和V族前体流入处理室，直到形成共形层，同时停止III族前体的流动，将处理室加热至退火温度，并将处理室冷却至第二温度。 可以通过使用优先蚀刻电介质区域的卤化物气蚀刻来选择性地制备III / V层的沉积。

公开(公告)号：US20110253982A1

公开(公告)日：2011-10-20

申请号：US13126381

申请日：2009-10-28

申请人： Deli Wang ,  Cesare Soci ,  Xinyu Bao ,  Wei Wei ,  Yi Jing ,  Ke Sun

发明人： Deli Wang ,  Cesare Soci ,  Xinyu Bao ,  Wei Wei ,  Yi Jing ,  Ke Sun

IPC分类号： H01L29/775 ,  H01L21/20 ,  H01L29/66 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L21/0262 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/02636 ,  H01L27/0605 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/7784 ,  H01L29/88 ,  H01L31/035281 ,  H01L31/03529 ,  H01L31/074 ,  H01L33/08 ,  H01L33/20 ,  H01L33/32 ,  Y02E10/50 ,  Y10S438/938 ,  Y10S438/967 ,  Y10S438/974 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764 ,  Y10S977/765 ,  Y10S977/813 ,  Y10S977/815 ,  Y10S977/819 ,  Y10S977/825

摘要： Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures. An array of Group III-V nanowire structures is embedded in polymer. A fabrication method forms the vertical nanowires on a substrate, e.g., a silicon substrate. Preferably, the nanowires are formed by the preferred methods for fabrication of Group III-V nanowires on silicon. Devices can be formed with core/shell and core/multi-shell nanowires and the devices are released from the substrate upon which the nanowires were formed to create a flexible structure that includes an array of vertical nanowires embedded in polymer.

摘要翻译： 本发明的实施例提供了一种在硅衬底上直接异质外延生长垂直III-V半导体纳米线的方法。 蚀刻硅衬底以基本上完​​全去除天然氧化物。 将其迅速置于反应室中。 将基底加热并保持在生长温度。 III-V族前体流过生长时间。 优选的实施例中，硅上的垂直III-V族III族纳米线具有核 - 壳结构，其提供径向同态结或异质结。 掺杂的纳米线芯由具有互补掺杂的壳包围。 这样可以由于在垂直的纳米线的轴向方向上的长的光路而提供高的光学吸收，同时在径向方向收集载体之前要大大减小载体必须扩散的距离。 合金成分也可以变化。 可以实现径向和轴向同态和异质结。 实施例提供柔性III-V族纳米线结构。 III-V族纳米线结构阵列嵌入聚合物中。 制造方法在衬底（例如，硅衬底）上形成垂直的纳米线。 优选地，通过在硅上制造III-V族III族纳米线的优选方法形成纳米线。 器件可以用核/壳和核/多壳纳米线形成，并且器件从其上形成纳米线的衬底释放以产生包括嵌入聚合物中的垂直纳米线阵列的柔性结构。

公开(公告)号：US08426224B2

公开(公告)日：2013-04-23

申请号：US12520082

申请日：2007-12-18

申请人： Deli Wang ,  Xinyu Bao ,  Bin Xiang ,  Cesare Soci ,  David Aplin

发明人： Deli Wang ,  Xinyu Bao ,  Bin Xiang ,  Cesare Soci ,  David Aplin

IPC分类号： H01L21/00

CPC分类号： H01L33/18 ,  B82Y20/00 ,  B82Y30/00 ,  H01L33/24 ,  H01S5/1042 ,  H01S5/183 ,  H01S5/423

摘要： Semiconductor nanowire arrays are used to replace the conventional planar layered construction for fabrication of LEDs and laser diodes. The nanowire arrays are formed from III-V or II-VI compound semiconductors on a conducting substrate. For fabrication of the device, an electrode layer is deposited on the substrate, a core material of one of a p-type and n-type compound semiconductor material is formed on top of the electrode as a planar base with a plurality of nanowires extending substantially vertically therefrom. A shell material of the other of the p-type and n-type compound semiconductor material is formed over an outer surface of the core material so that a p-n junction is formed across the planar base and over each of the plurality of nanowires. An electrode coating is formed an outer surface of the shell material for providing electrical contact to a current source. Heterostructures and superlattices grown along the lengths of the nanowires allow the confinement of photons in the quantum well to enhance the efficiency and as well as color tuning.

摘要翻译： 半导体纳米线阵列用于替代用于制造LED和激光二极管的常规平面分层结构。 纳米线阵列由导电衬底上的III-V或II-VI化合物半导体形成。 为了制造器件，在衬底上沉积电极层，在电极顶部形成p型和n型化合物半导体材料之一的芯材作为平面基底，其中多个纳米线基本上延伸 垂直地。 p型和n型化合物半导体材料中的另一种的外壳材料形成在芯材的外表面上，从而跨平面基底和多个纳米线中的每一个形成p-n结。 电极涂层形成外壳材料的外表面，用于提供与电流源的电接触。 沿着纳米线的长度生长的异质结构和超晶格允许光子在量子阱中的约束以提高效率以及颜色调整。

公开(公告)号：US20110163292A1

公开(公告)日：2011-07-07

申请号：US12520082

申请日：2007-12-18

申请人： Deli Wang ,  Xinyu Bao ,  Bin Xiang ,  Cesare Soci ,  David Aplin

发明人： Deli Wang ,  Xinyu Bao ,  Bin Xiang ,  Cesare Soci ,  David Aplin

IPC分类号： H01L33/06 ,  H01L33/30 ,  H01L33/28 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L33/18 ,  B82Y20/00 ,  B82Y30/00 ,  H01L33/24 ,  H01S5/1042 ,  H01S5/183 ,  H01S5/423

摘要： Semiconductor nanowire arrays are used to replace the conventional planar layered construction for fabrication of LEDs and laser diodes. The nanowire arrays are formed from III-V or II-VI compound semiconductors on a conducting substrate. For fabrication of the device, an electrode layer is deposited on the substrate, a core material of one of a p-type and n-type compound semiconductor material is formed on top of the electrode as a planar base with a plurality of nanowires extending substantially vertically therefrom. A shell material of the other of the p-type and n-type compound semiconductor material is formed over an outer surface of the core material so that a p-n junction is formed across the planar base and over each of the plurality of nanowires. An electrode coating is formed an outer surface of the shell material for providing electrical contact to a current source. Heterostructures and superlattices grown along the lengths of the nanowires allow the confinement of photons in the quantum well to enhance the efficiency and as well as color tuning.

摘要翻译： 半导体纳米线阵列用于替代用于制造LED和激光二极管的常规平面分层结构。 纳米线阵列由导电衬底上的III-V或II-VI化合物半导体形成。 为了制造器件，在衬底上沉积电极层，在电极的顶部上形成p型和n型化合物半导体材料之一的芯材作为平面基底，其中多个纳米线基本上延伸 垂直地。 p型和n型化合物半导体材料中的另一种的外壳材料形成在芯材的外表面上，从而跨平面基底和多个纳米线中的每一个形成p-n结。 电极涂层形成外壳材料的外表面，用于提供与电流源的电接触。 沿着纳米线的长度生长的异质结构和超晶格允许光子在量子阱中的约束以提高效率以及颜色调整。

公开(公告)号：US08932940B2

公开(公告)日：2015-01-13

申请号：US13126381

申请日：2009-10-28

申请人： Deli Wang ,  Cesare Soci ,  Xinyu Bao ,  Wei Wei ,  Yi Jing ,  Ke Sun

发明人： Deli Wang ,  Cesare Soci ,  Xinyu Bao ,  Wei Wei ,  Yi Jing ,  Ke Sun

IPC分类号： H01L21/20 ,  H01L21/02 ,  B82Y10/00 ,  H01L27/06 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/778 ,  H01L29/88 ,  H01L31/0352 ,  H01L31/074 ,  H01L33/20 ,  H01L33/08 ,  H01L33/32

CPC分类号： H01L21/0262 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/02636 ,  H01L27/0605 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/20 ,  H01L29/205 ,  H01L29/267 ,  H01L29/7784 ,  H01L29/88 ,  H01L31/035281 ,  H01L31/03529 ,  H01L31/074 ,  H01L33/08 ,  H01L33/20 ,  H01L33/32 ,  Y02E10/50 ,  Y10S438/938 ,  Y10S438/967 ,  Y10S438/974 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764 ,  Y10S977/765 ,  Y10S977/813 ,  Y10S977/815 ,  Y10S977/819 ,  Y10S977/825

摘要： Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures. An array of Group III-V nanowire structures is embedded in polymer. A fabrication method forms the vertical nanowires on a substrate, e.g., a silicon substrate. Preferably, the nanowires are formed by the preferred methods for fabrication of Group III-V nanowires on silicon. Devices can be formed with core/shell and core/multi-shell nanowires and the devices are released from the substrate upon which the nanowires were formed to create a flexible structure that includes an array of vertical nanowires embedded in polymer.

摘要翻译： 本发明的实施例提供了一种在硅衬底上直接异质外延生长垂直III-V半导体纳米线的方法。 蚀刻硅衬底以基本上完​​全去除天然氧化物。 将其迅速置于反应室中。 将基底加热并保持在生长温度。 III-V族前体流过生长时间。 优选的实施例中，硅上的垂直III-V族III族纳米线具有核 - 壳结构，其提供径向同态结或异质结。 掺杂的纳米线芯由具有互补掺杂的壳包围。 这样可以由于在垂直的纳米线的轴向方向上的长的光路而提供高的光学吸收，同时在径向方向收集载体之前要大大减小载体必须扩散的距离。 合金成分也可以变化。 可以实现径向和轴向同态和异质结。 实施例提供柔性III-V族纳米线结构。 III-V族纳米线结构阵列嵌入聚合物中。 制造方法在衬底（例如，硅衬底）上形成垂直的纳米线。 优选地，通过在硅上制造III-V族III族纳米线的优选方法形成纳米线。 器件可以用核/壳和核/多壳纳米线形成，并且器件从其上形成纳米线的衬底释放以产生包括嵌入聚合物中的垂直纳米线阵列的柔性结构。