公开(公告)号：US20050124151A1

公开(公告)日：2005-06-09

申请号：US10728215

申请日：2003-12-04

申请人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

发明人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819

摘要： A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.

摘要翻译： 公开了一种用于在CVD室中沉积黑金刚石层的方法。 三甲基硅烷O 2和Ar在300℃至400℃下以0:2:Ar:三甲基硅烷流速比流入室中，优选 1：1.5：6。 形成的低k电介质层的沉积速率高于省略Ar时的沉积速率，并且具有约3的K值仅在O 2等离子体中略微增加。 当在沉积过程中包含Ar时，在黑色金刚石层中获得较高的密度，硬度和拉伸强度。 沉积中Ar的添加将膜厚度均匀性维持在2％以下更长的时间，以便PM清洁操作较不频繁，并提供较低的氟碳等离子体蚀刻速率，从而能够改进镶嵌方案中的沟槽深度控制。 在所得到的金属互连中实现较低的漏电流和更高的击穿电压。

公开(公告)号：US07157367B2

公开(公告)日：2007-01-02

申请号：US10861149

申请日：2004-06-04

申请人： Hway Chi Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

发明人： Hway Chi Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).

摘要翻译： 提供了一种衬底，其具有形成在衬底中和衬底上的半导体器件结构。 半导体器件结构包括嵌入介电常数小于4.5的电介质层的开口中的导体层。 电介质层在电介质和导体之间具有粗糙度，其中介电层的粗糙度除以导体层下面的阻挡层的厚度为0-1。集成电路结构通过去除低电介质来制备用于故障分析 恒电介质层，并通过光学检查或扫描电子显微镜（SEM）暴露导体层进行进一步的故障分析。

公开(公告)号：US07449911B2

公开(公告)日：2008-11-11

申请号：US11729759

申请日：2007-03-29

申请人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

发明人： Yi-Lung Cheng ,  Bi-Ling Liu ,  Chin-Chuang Peng ,  Chien-Shih Tsai ,  Hway-Chi Lin

IPC分类号： G01R31/26

CPC分类号： G01R31/2858

摘要： A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.

摘要翻译： 一种用于测试集成电路的方法包括形成多个基本上相同的第一测试结构，每个第一测试结构包括连接到第一金属线的第一通孔结构，测试多个第一测试结构以获得第一多个故障时间，以及形成 多个基本上相同的第二测试结构，每个包括连接到第二金属线的第二通孔结构，其中第二通孔结构具有与第一通孔结构基本上不同的可靠性，并且其中第一金属线和第二金属线基本相同 相同。 该方法还包括对多个第二测试结构进行压力测试以获得第二多个故障时间，以及确定多个第一测试结构和多个第二测试结构的早期故障。

公开(公告)号：US20080184805A1

公开(公告)日：2008-08-07

申请号：US11729759

申请日：2007-03-29

申请人： Yi-Lung Cheng ,  BL Lin ,  CC Peng ,  C.S. Tsai ,  Hway-Chi Lin

发明人： Yi-Lung Cheng ,  BL Lin ,  CC Peng ,  C.S. Tsai ,  Hway-Chi Lin

IPC分类号： G01N3/00

CPC分类号： G01R31/2858

摘要： A method for testing integrated circuits includes forming a plurality of substantially identical first test structures, each comprising a first via structure connected to a first metal line, stress testing the plurality of first test structures to obtain a first plurality of failure times, and forming a plurality of substantially identical second test structures, each comprising a second via structure connected to a second metal line, wherein the second via structure has a substantially different reliability from the first via structure, and wherein the first metal line and the second metal line are substantially identical. The method further includes stress testing the plurality of second test structures to obtain a second plurality of failure times, and determining early failures of the plurality of first test structures and the plurality of second test structures.

摘要翻译： 一种用于测试集成电路的方法包括形成多个基本上相同的第一测试结构，每个第一测试结构包括连接到第一金属线的第一通孔结构，测试多个第一测试结构以获得第一多个故障时间，以及形成 多个基本上相同的第二测试结构，每个包括连接到第二金属线的第二通孔结构，其中第二通孔结构具有与第一通孔结构基本上不同的可靠性，并且其中第一金属线和第二金属线基本相同 相同。 该方法还包括对多个第二测试结构进行压力测试以获得第二多个故障时间，以及确定多个第一测试结构和多个第二测试结构的早期故障。

公开(公告)号：US06479098B1

公开(公告)日：2002-11-12

申请号：US09747135

申请日：2000-12-26

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1640

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

摘要翻译： 一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。 腔室等离子体处理区域部件被清洁。 然后如下调节室。 在室等离子体处理区域部件上形成第一USG层。 在第一USG层上形成FSG层。 在FSG层上形成第二个USG层。 其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

公开(公告)号：US07125802B2

公开(公告)日：2006-10-24

申请号：US10696432

申请日：2003-10-29

申请人： Ying-Lang Wang ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Chi-Wen Liu ,  Ming-Hua Yoo ,  Wen-Kung Cheng ,  Jiann-Kwang Wang

发明人： Ying-Lang Wang ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Chi-Wen Liu ,  Ming-Hua Yoo ,  Wen-Kung Cheng ,  Jiann-Kwang Wang

IPC分类号： H01L21/306

CPC分类号： C09G1/02 ,  H01L21/3212 ,  H01L21/7684

摘要： Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

公开(公告)号：US20050106858A1

公开(公告)日：2005-05-19

申请号：US10716818

申请日：2003-11-19

申请人： Yi-Lung Cheng ,  Ying-Lang Wang

发明人： Yi-Lung Cheng ,  Ying-Lang Wang

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76831

摘要： A method is disclosed for reducing metal diffusion in a semiconductor device. After forming a first metal portion over a substrate, a silicon carbon nitro-oxide (SiCNO) layer is deposited on the first metal portion. A dielectric layer is deposited over the SiCNO layer, and an opening is generated in the SiCNO layer and the dielectric layer for a second metal portion to be connected to the first metal portion, wherein the SiCNO layer reduces the diffusion of the first metal portion into the dielectric layer.

摘要翻译： 公开了一种用于减少半导体器件中的金属扩散的方法。 在衬底上形成第一金属部分之后，在第一金属部分上沉积硅碳氧化物（SiCNO）层。 在SiCNO层上沉积介电层，在SiCNO层和第二金属部分的介电层上产生开口以连接到第一金属部分，其中SiCNO层将第一金属部分的扩散减少到 电介质层。

公开(公告)号：US06802935B2

公开(公告)日：2004-10-12

申请号：US10103618

申请日：2002-03-21

申请人： Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Yi-Lung Cheng ,  Hui-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： B65G4907

CPC分类号： H01L21/67167 ,  C23C16/4405 ,  C23C16/54 ,  H01L21/67196 ,  Y10S414/135

摘要： A semiconductor processing apparatus and method are disclosed herein, including a plurality of process chambers, wherein at least one semiconductor processing operation occurs within each process chamber among the plurality of process chambers. Additionally, the apparatus and method disclosed herein include a robot mechanism for rotating each process chamber among the plurality of process chambers upon completion of an associated semiconductor processing operation. Such a robot mechanism may comprise a plurality of robots. Specifically, such a plurality of robots may include six robots configured on an associated carousel.

摘要翻译： 本文公开了包括多个处理室的半导体处理装置和方法，其中在多个处理室中的每个处理室内发生至少一个半导体处理操作。 此外，本文公开的装置和方法包括机器人机构，用于在完成相关联的半导体处理操作时在多个处理室中旋转每个处理室。 这样的机器人机构可以包括多个机器人。 具体地说，这样的多个机器人可以包括配置在相关转盘上的六个机器人。

公开(公告)号：US07253121B2

公开(公告)日：2007-08-07

申请号：US10937215

申请日：2004-09-09

申请人： Yi-Lung Cheng ,  Miao-Cheng Liao ,  Ying-Lang Wang

发明人： Yi-Lung Cheng ,  Miao-Cheng Liao ,  Ying-Lang Wang

IPC分类号： H01L21/471

CPC分类号： H01L21/76807

摘要： A method for forming IMD films. A substrate is provided. A plurality of dielectric films are formed on the substrate, wherein each of the dielectric layers are deposited in-situ in one chamber with only one thermal cycle.

摘要翻译： 一种形成IMD膜的方法。 提供基板。 在基板上形成多个电介质膜，其中每个电介质层原位沉积在仅具有一个热循环的一个室中。

公开(公告)号：US06790778B1

公开(公告)日：2004-09-14

申请号：US10658270

申请日：2003-09-10

申请人： Yi-Lung Cheng ,  Ying-Lang Wang ,  We-Li Chen

发明人： Yi-Lung Cheng ,  Ying-Lang Wang ,  We-Li Chen

IPC分类号： H01L2144

CPC分类号： H01L21/76834 ,  H01L21/76883 ,  Y10S438/902 ,  Y10S438/906

摘要： A method for capping over a copper layer. A copper layer is deposited overlying a substrate. The copper surface is treated with hydrogen-containing plasma to remove copper oxides formed thereon, thereby suppressing copper hillock formation. The treated copper surface is treated again with nitrogen-containing plasma to improve adhesion of the copper surface. A capping layer is formed on the copper layer.

摘要翻译： 一种覆盖铜层的方法。 将铜层沉积在衬底上。 用含氢等离子体处理铜表面以除去其上形成的铜氧化物，从而抑制铜形成小丘。 处理的铜表面再次用含氮等离子体处理以改善铜表面的粘附。 在铜层上形成覆盖层。