公开(公告)号：US06514673B2

公开(公告)日：2003-02-04

申请号：US09818962

申请日：2001-03-28

申请人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

发明人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

IPC分类号： G03F700

CPC分类号： B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224

摘要： A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

公开(公告)号：US06232043B1

公开(公告)日：2001-05-15

申请号：US09318471

申请日：1999-05-25

申请人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

发明人： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

IPC分类号： G03F700

CPC分类号： B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224

摘要： A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

摘要翻译： 描述了一种用于计算在CMP期间需要去除的HDP沉积材料的最佳量的简单方法（不引入凹陷）。 该方法来源于我们观察到需要去除的材料的量之间的线性关系以实现完全平坦化，并且称为“用于CMP密度的OD”。 后者被定义为PAx（100-PS），其中PA是相对于总晶片面积的有效面积的百分比，PS是相对于总晶片面积的子区域的百分比。 子区域是在CMP之前被蚀刻出的有源区域之上的电介质区域。 因此，一旦材料被表征，就可以很容易地计算各种不同电路实现的最佳CMP去除厚度。

公开(公告)号：US06291872B1

公开(公告)日：2001-09-18

申请号：US09433255

申请日：1999-11-04

申请人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

发明人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

IPC分类号： H01L2900

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01L27/08

摘要： Vertical type structures for integrated circuit inductors are disclosed. These vertical type inductors include the single-loop type, the parallel-loop type and the screw type, which form three different embodiments in the present invention. In the first embodiment, three-dimensional type structures, a single-loop type is utilized as an integrated circuit inductor. This inductor structure is formed on a substrate and the axis of the structure is upright to the substrate. In another embodiment according to the present invention, a parallel-loop type structure for radio frequency (RF) integrated circuit inductor is provided. A screw type structure according to this invention is the third embodiment. It features an axis that is parallel to the surface of the substrate and threads into the semiconductor device.

摘要翻译： 公开了集成电路电感器的垂直型结构。 这些垂直型电感器包括在本发明中形成三个不同实施例的单环型，并联环型和螺旋型。 在第一实施例中，采用单环型的三维型结构作为集成电路电感器。 该电感器结构形成在基板上，并且该结构的轴线垂直于基板。 在根据本发明的另一实施例中，提供了一种用于射频（RF）集成电路电感器的并联环路结构。 根据本发明的螺杆型结构是第三实施例。 它具有平行于衬底表面并进入半导体器件的轴线。

公开(公告)号：US20050124151A1

公开(公告)日：2005-06-09

申请号：US10728215

申请日：2003-12-04

申请人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

发明人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819

摘要： A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.

摘要翻译： 公开了一种用于在CVD室中沉积黑金刚石层的方法。 三甲基硅烷O 2和Ar在300℃至400℃下以0:2:Ar:三甲基硅烷流速比流入室中，优选 1：1.5：6。 形成的低k电介质层的沉积速率高于省略Ar时的沉积速率，并且具有约3的K值仅在O 2等离子体中略微增加。 当在沉积过程中包含Ar时，在黑色金刚石层中获得较高的密度，硬度和拉伸强度。 沉积中Ar的添加将膜厚度均匀性维持在2％以下更长的时间，以便PM清洁操作较不频繁，并提供较低的氟碳等离子体蚀刻速率，从而能够改进镶嵌方案中的沟槽深度控制。 在所得到的金属互连中实现较低的漏电流和更高的击穿电压。

公开(公告)号：US09419155B2

公开(公告)日：2016-08-16

申请号：US13343922

申请日：2012-01-05

申请人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L31/0232 ,  H01L31/101 ,  H01L31/18

CPC分类号： H01L31/0232 ,  H01L31/02327 ,  H01L31/101 ,  H01L31/18

摘要： This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 μm.

摘要翻译： 该描述涉及使用具有多个外延层的基板形成的感测产品。 至少第一外延层具有与第二外延层的组成不同的组成。 感测产品可选地包括第二外延层中的至少一个辐射感测元件以及可选地在第二外延层上的互连结构。 通过去除衬底和除第二外延层之外的所有外延层形成传感产物。 第二外延层的光入射表面具有小于约0.15μm的总厚度变化。

公开(公告)号：US07312149B2

公开(公告)日：2007-12-25

申请号：US10840095

申请日：2004-05-06

申请人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

发明人： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

IPC分类号： H01L21/44

CPC分类号： C25D7/123 ,  C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  H01L21/2885

摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

摘要翻译： 在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀 从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。 第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。 低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

公开(公告)号：US06863491B2

公开(公告)日：2005-03-08

申请号：US10339691

申请日：2003-01-08

申请人： Hsi-Kuei Cheng ,  Chun-Tse Lin ,  Ting-Chun Wang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Hsi-Kuei Cheng ,  Chun-Tse Lin ,  Ting-Chun Wang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/687 ,  B23B31/16

CPC分类号： H01L21/68707 ,  Y10T279/1033 ,  Y10T279/1291 ,  Y10T279/19

摘要： A new and improved wafer support for supporting wafers in a process chamber such as an edge bead removal (EBR) chamber. The wafer support comprises multiple wafer support units each including a gripper block that engages an edge portion or bevel of the wafer. The gripper block is attached to an engaging and disengaging mechanism for selectively causing engagement of the gripper blocks with the wafer to support the wafer and disengagement of the gripper blocks from the wafer to release the wafer for removal of the wafer from the chamber. The gripper blocks contact little or none of the surface area on the patterned surface of the wafer to prevent or substantially reduce the formation of contact-induced defects on the wafer.

摘要翻译： 一种新的和改进的晶片支撑件，用于在诸如边缘珠去除（EBR）室的处理室中支撑晶片。 晶片支撑件包括多个晶片支撑单元，每个晶片支撑单元包括接合晶片的边缘部分或斜面的夹持块。 夹持块附接到接合和分离机构，用于选择性地使夹持器块与晶片接合以支撑晶片，并且将夹持器块与晶片分离，以释放晶片以从晶片移除。 夹持器块几乎不接触晶片的图案化表面上的表面积，以防止或基本上减少晶片上接触引起的缺陷的形成。

公开(公告)号：US06352924B1

公开(公告)日：2002-03-05

申请号：US09587463

申请日：2000-06-05

申请人： Jun Wu ,  Ming Jer Lee ,  Yu Ku Lin ,  Ying-Lang Wang

发明人： Jun Wu ,  Ming Jer Lee ,  Yu Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L2144

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877

摘要： A new method is provided to replace tungsten plugs for wafers that trigger the WCVD backside alarm. In this new rework process, the original TiN glue layer is sputter etched back and a new (“fresh”) 100-Angstrom thick layer of TiN is deposited. The new tungsten plug is created over the top surface of the refreshed glue layer.

摘要翻译： 提供了一种新方法来替代触发WCVD背面报警的晶片的钨丝塞。 在这种新的返工过程中，将原始TiN胶层溅射回蚀刻，并沉积出新的（“新鲜”）100埃厚的TiN层。 新的钨丝塞在刷新的胶层的上表面上形成。

公开(公告)号：US6099662A

公开(公告)日：2000-08-08

申请号：US248726

申请日：1999-02-11

申请人： Ying-Lang Wang ,  Jowei Dun ,  Ken-Shen Chou ,  Yu-Ku Lin

发明人： Ying-Lang Wang ,  Jowei Dun ,  Ken-Shen Chou ,  Yu-Ku Lin

IPC分类号： H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  B08B3/00 ,  H01L21/00

CPC分类号： H01L21/02065 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/3212

摘要： An improved method for removing residual slurry particles and metallic residues from the surface of a semiconductor substrate after chemical-mechanical polishing has been developed. The cleaning method involves sequential spray cleaning solutions of NH.sub.4 OH and H.sub.2 O, NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, HF and H.sub.2 O, and HCl, H.sub.2 O.sub.2 and H.sub.2 O. The cleaning sequence is: 1. A pre-soak in a spray solution of NH.sub.4 OH and H.sub.2 O; 2. Spray cleaning in a solution of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O; 3. Spray cleaning in a dilute solution of HF and H.sub.2 O; 4. Spray rinsing in DI-water. It is important that slurry particulates first be removed by NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, followed by spray cleaning in a dilute solution of HF and H.sub.2 O to remove metallic residues. The spray cleaning method is superior to brush cleaning methods for both oxide-CMP and tungsten-CMP and results in superior removal of slurry particles and metallic residues introduced by the CMP processes. An optional spray cleaning step using a solution of HCl, H.sub.2 O.sub.2 and H.sub.2 O results in further reduction of metallic residue contamination following oxide-CMP. Compared to traditional brush cleaning the new spray cleaning process has a 2.times. improvement in throughput, less consumption of DI water, and low risk of cross-contamination between sequentially cleaned substrates.

摘要翻译： 已经开发了用于在化学机械抛光之后从半导体衬底的表面除去残余浆料颗粒和金属残留物的改进方法。 清洗方法包括NH 4 OH和H 2 O，NH 4 OH，H 2 O 2和H 2 O，HF和H 2 O以及HCl，H 2 O 2和H 2 O的顺序喷雾清洗溶液。 清洗顺序为：1.在NH4OH和H2O的喷雾溶液中预浸泡; 2.在NH4OH，H2O2和H2O溶液中喷雾清洗; 3.在HF和H2O的稀溶液中喷雾清洗; 4.在DI水中喷淋。 重要的是，首先通过NH 4 OH，H 2 O 2和H 2 O除去浆料颗粒，然后在HF和H 2 O的稀溶液中喷雾清洗以除去金属残余物。 喷雾清洗方法优于氧化物CMP和钨-CMP两者的刷子清洗方法，并且优异地除去由CMP工艺引入的浆料颗粒和金属残留物。 使用HCl，H2O2和H2O溶液的可选喷雾清洗步骤可以进一步降低氧化物CMP后的金属残留污染。 与传统的刷子清洁相比，新的喷雾清洁过程在吞吐量方面有2倍的改善，更少的去离子水消耗，以及顺序清洗的基材之间交叉污染的风险较低。

公开(公告)号：US20130126950A1

公开(公告)日：2013-05-23

申请号：US13304235

申请日：2011-11-23

申请人： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L23/53209 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.