利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

70 条记录 (耗时 0.052 秒)

    SIMULATION METHOD FOR IMPROVING FREEDOM OF SETTING PARAMETERS RELATING TO INPUT/OUTPUT CHARACTERISTICS OF A MEMORY CHIP
    1.
    发明申请
    SIMULATION METHOD FOR IMPROVING FREEDOM OF SETTING PARAMETERS RELATING TO INPUT/OUTPUT CHARACTERISTICS OF A MEMORY CHIP 审中-公开
    用于改进与存储芯片的输入/输出特性相关的设置参数自由的模拟方法

    公开(公告)号：US20080040081A1

    公开(公告)日：2008-02-14

    申请号：US11676183

    申请日：2007-02-16

    申请人： Yoji NISHIO ,  Seiji Funaba ,  Yurika Aoki ,  Kazuyoshi Shoji ,  Koji Matsuo ,  Mariko Otsuka ,  Ryuichi Ikematsu ,  Sadahiro Nonoyama ,  Kae Fujii

    发明人： Yoji NISHIO ,  Seiji Funaba ,  Yurika Aoki ,  Kazuyoshi Shoji ,  Koji Matsuo ,  Mariko Otsuka ,  Ryuichi Ikematsu ,  Sadahiro Nonoyama ,  Kae Fujii

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009

    摘要： In the simulation method of the present invention; one parameter is first selected from a plurality of parameters that relate to input/output characteristics. Next, regarding setting lines provided in a file for setting necessary choices from among a plurality of choices for a selected parameter, it is determined to either set choices by means of comment symbols that cause non-execution of the relevant lines, or set choices by means of identification codes, which are identifiers common to chips in which the same choice are to be set. When choices are to be set by means of comment symbols, the comment symbols of the setting lines of the necessary choices among the plurality of choices are deleted to make these setting lines effective. Alternatively, when choices are to be set by means of identification codes, the identification codes included in setting lines are rewritten to information for setting to the necessary choices. Finally, the simulation is executed.

    摘要翻译： 在本发明的模拟方法中， 首先从与输入/输出特性相关的多个参数中选择一个参数。 接下来，关于设置在文件中的设置线，用于从所选择的参数的多个选择中设置必要的选择，确定通过引起不执行相关行的注释符号设置选择，或者通过 识别码的装置，它们是与要设置相同选择的芯片通用的标识符。 当通过注释符号来设置选择时，删除多个选择中必要选择的设置行的注释符号，使得这些设置行成为有效。 或者，当通过识别码设置选择时，将包括在设定线中的识别码重写为用于设置为必要选择的信息。 最后，执行仿真。

    Memory module with load capacitance added to clock signal input
    2.
    发明授权
    Memory module with load capacitance added to clock signal input 失效
    负载电容加到时钟信号输入的存储模块

    公开(公告)号：US07656744B2

    公开(公告)日：2010-02-02

    申请号：US11611036

    申请日：2006-12-14

    申请人： Yurika Aoki ,  Seiji Funaba ,  Yoji Nishio

    发明人： Yurika Aoki ,  Seiji Funaba ,  Yoji Nishio

    IPC分类号： G11C8/00

    CPC分类号： G11C5/063 ,  G11C5/04

    摘要： A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.

    摘要翻译： 提供了具有多级配置的新型存储器模块，以解决由于输入到存储器的数据选通信号的定时偏离输入到其的时钟信号的定时的事实而无法进行高速操作的问题。 在存储器模块中，在锁存环路电路的时钟信号输入引脚附近提供负载能力，其中输入时钟信号以使数据选通信号线的时间常数与时钟的时间常数相匹配 信号线。 时钟信号的输入定时和输入到存储器的数据选通信号的匹配使得存储器模块能够以高速运行。

    MEMORY MODULE
    3.
    发明申请
    MEMORY MODULE 失效
    记忆模块

    公开(公告)号：US20070140040A1

    公开(公告)日：2007-06-21

    申请号：US11611036

    申请日：2006-12-14

    申请人： Yurika Aoki ,  Seiji Funaba ,  Yoji Nishio

    发明人： Yurika Aoki ,  Seiji Funaba ,  Yoji Nishio

    IPC分类号： G11C5/06 ,  G11C8/00

    CPC分类号： G11C5/063 ,  G11C5/04

    摘要： A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.

    摘要翻译： 提供了具有多级配置的新型存储器模块，以解决由于输入到存储器的数据选通信号的定时偏离输入到其的时钟信号的定时的事实而无法进行高速操作的问题。 在存储器模块中，在锁存环路电路的时钟信号输入引脚附近提供负载能力，其中输入时钟信号以使数据选通信号线的时间常数与时钟的时间常数相匹配 信号线。 时钟信号的输入定时和输入到存储器的数据选通信号的匹配使得存储器模块能够以高速运行。

    SEMICONDUCTOR DEVICE, MEMORY DEVICE AND MEMORY MODULE HAVING DIGITAL INTERFACE
    4.
    发明申请
    SEMICONDUCTOR DEVICE, MEMORY DEVICE AND MEMORY MODULE HAVING DIGITAL INTERFACE 有权
    半导体器件，存储器件和具有数字接口的存储器模块

    公开(公告)号：US20090245424A1

    公开(公告)日：2009-10-01

    申请号：US12481798

    申请日：2009-06-10

    申请人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    发明人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    IPC分类号： H03K9/00

    CPC分类号： H03K5/082 ,  H03K5/135

    摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

    摘要翻译： 本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。 本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。 由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收机接收到的数据的状态，并根据保持的状态和输入来调整提取输入数据的定时 数据。 作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。 接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

    Semiconductor device, memory device and memory module having digital interface
    5.
    发明授权
    Semiconductor device, memory device and memory module having digital interface 失效
    半导体器件，存储器件和具有数字接口的存储器模块

    公开(公告)号：US07558336B2

    公开(公告)日：2009-07-07

    申请号：US10982946

    申请日：2004-11-08

    申请人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    发明人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    IPC分类号： H03K9/00 ,  H04B3/46 ,  G06K5/04 ,  H03M13/00 ,  G06F13/42

    CPC分类号： H03K5/082 ,  H03K5/135

    摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

    摘要翻译： 本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。 本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。 由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收器接收到的数据的状态，并且根据保持的状态和输入来调整提取输入数据的定时 数据。 作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。 接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

    Semiconductor device, memory device and memory module having digital interface
    6.
    发明申请
    Semiconductor device, memory device and memory module having digital interface 失效

    公开(公告)号：US20060018407A1

    公开(公告)日：2006-01-26

    申请号：US10982946

    申请日：2004-11-08

    申请人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    发明人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    IPC分类号： H03K9/00

    CPC分类号： H03K5/082 ,  H03K5/135

    摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

    Semiconductor device, memory device and memory module having digital interface
    7.
    发明授权
    Semiconductor device, memory device and memory module having digital interface 有权
    半导体器件，存储器件和具有数字接口的存储器模块

    公开(公告)号：US07856072B2

    公开(公告)日：2010-12-21

    申请号：US12481798

    申请日：2009-06-10

    申请人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    发明人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    IPC分类号： H03K9/00 ,  H03B1/00 ,  G05F1/10

    CPC分类号： H03K5/082 ,  H03K5/135

    摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

    摘要翻译： 本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。 本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。 由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收器接收到的数据的状态，并且根据保持的状态和输入来调整提取输入数据的定时 数据。 作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。 接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

    Memory module and memory system
    8.
    发明授权
    Memory module and memory system 有权
    内存模块和内存系统

    公开(公告)号：US07411806B2

    公开(公告)日：2008-08-12

    申请号：US11634405

    申请日：2006-12-06

    申请人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

    发明人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

    IPC分类号： G11C5/06 ,  G11C5/02

    CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C11/4093 ,  G11C2207/105 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107

    摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

    摘要翻译： 存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。 总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线 孔（119）用于使线路循环。 设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。 该存储器模块通过连接器安装在其上提供存储器控制器的母板上。 母线的有效特性阻抗与母板线路特性阻抗匹配。