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    Memory module and memory system
    1.
    发明授权
    Memory module and memory system 有权
    内存模块和内存系统

    公开(公告)号：US07411806B2

    公开(公告)日：2008-08-12

    申请号：US11634405

    申请日：2006-12-06

    申请人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

    发明人： Seiji Funaba ,  Yoji Nishio ,  Kayoko Shibata

    IPC分类号： G11C5/06 ,  G11C5/02

    CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C11/4093 ,  G11C2207/105 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107

    摘要： A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

    摘要翻译： 存储器模块具有在板的前表面和后表面上共享总线的多个DRAM（115）。 总线通过通孔（113）从端子（111）连接到带状线（112）的一端，并且带状线的另一端通过通孔（113）连接到另一层中的带状线 孔（119）用于使线路循环。 设置在终端电压端子（VTT）附近的终端电阻器（120）通过通孔连接到另一层中的环形带状线。 DRAM端子通过通孔连接到带状线。 该存储器模块通过连接器安装在其上提供存储器控制器的母板上。 母线的有效特性阻抗与母板线路特性阻抗匹配。

    Memory module including module data wirings available as a memory access data bus
    4.
    发明授权
    Memory module including module data wirings available as a memory access data bus 有权
    存储器模块包括可用作存储器访问数据总线的模块数据配线

    公开(公告)号：US06628538B2

    公开(公告)日：2003-09-30

    申请号：US10105249

    申请日：2002-03-26

    申请人： Seiji Funaba ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Yoji Nishio

    发明人： Seiji Funaba ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Yoji Nishio

    IPC分类号： G11C506

    CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/063 ,  H01L23/5387 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2924/01055 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011

    摘要： A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

    摘要翻译： 模块基板具有与多个存储器芯片中的各个芯片数据端子相关联地分别设置的多个模块数据端子对以及分别连接在多个模块数据端子对之间的多个模块数据布线。 多个模块数据布线连接到它们对应的芯片数据终端，并被配置为可用作存储器访问数据总线。 在并行布置多个存储器模块的存储器系统中，各个存储器模块的模块数据布线以串行形式连接，并且每个单独的模块数据布线不构成相对于主板上的数据总线的分支布线 的内存系统。 在存储器模块中，确保与存储器访问数据总线的宽度相对应的位数的并行访问。

    Stacked semiconductor device
    6.
    发明授权
    Stacked semiconductor device 有权
    堆叠半导体器件

    公开(公告)号：US07768867B2

    公开(公告)日：2010-08-03

    申请号：US11761470

    申请日：2007-06-12

    申请人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

    发明人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

    IPC分类号： G11C8/00

    CPC分类号： G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

    摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

    摘要翻译： 叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘 存储芯片12。

    SEMICONDUCTOR DEVICE, MEMORY DEVICE AND MEMORY MODULE HAVING DIGITAL INTERFACE
    7.
    发明申请
    SEMICONDUCTOR DEVICE, MEMORY DEVICE AND MEMORY MODULE HAVING DIGITAL INTERFACE 有权
    半导体器件，存储器件和具有数字接口的存储器模块

    公开(公告)号：US20090245424A1

    公开(公告)日：2009-10-01

    申请号：US12481798

    申请日：2009-06-10

    申请人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    发明人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    IPC分类号： H03K9/00

    CPC分类号： H03K5/082 ,  H03K5/135

    摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

    摘要翻译： 本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。 本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。 由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收机接收到的数据的状态，并根据保持的状态和输入来调整提取输入数据的定时 数据。 作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。 接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

    Semiconductor device, memory device and memory module having digital interface
    8.
    发明授权
    Semiconductor device, memory device and memory module having digital interface 失效
    半导体器件，存储器件和具有数字接口的存储器模块

    公开(公告)号：US07558336B2

    公开(公告)日：2009-07-07

    申请号：US10982946

    申请日：2004-11-08

    申请人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    发明人： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

    IPC分类号： H03K9/00 ,  H04B3/46 ,  G06K5/04 ,  H03M13/00 ,  G06F13/42

    CPC分类号： H03K5/082 ,  H03K5/135

    摘要： An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

    摘要翻译： 本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。 本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。 由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收器接收到的数据的状态，并且根据保持的状态和输入来调整提取输入数据的定时 数据。 作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。 接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

    Semiconductor integrated circuit and electronic device
    9.
    发明授权
    Semiconductor integrated circuit and electronic device 失效
    半导体集成电路和电子设备

    公开(公告)号：US07478287B2

    公开(公告)日：2009-01-13

    申请号：US11270608

    申请日：2005-11-10

    申请人： Seiji Funaba ,  Yoji Nishio

    发明人： Seiji Funaba ,  Yoji Nishio

    IPC分类号： G11B20/20 ,  G01R31/28 ,  G01R31/26

    CPC分类号： G11C7/22 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H05K1/0248 ,  H05K1/0268 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09781

    摘要： A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

    摘要翻译： 虚拟布线25用于模拟连接电路板上的半导体集成电路2和6的实际布线26。 半导体集成电路包括能够可变地设置转换速率的数据输出电路28和用于使用虚拟布线25测量信号发送点和信号反射点之间的信号延迟时间的电路29（特征阻抗失配点），并且 由测量电路获得的延迟时间用于确定输出电路的信号转换时间。 信号的转换时间设置为信号发送点和最近端的布线支路之间的信号延迟时间的至少两倍。 以这种方式，实现了由最近端的反射点减轻反射的信号传输。