公开(公告)号：US20090121323A1

公开(公告)日：2009-05-14

申请号：US12266748

申请日：2008-11-07

申请人： Yong-Chai KWON ,  Nam-Seong KIM

发明人： Yong-Chai KWON ,  Nam-Seong KIM

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including an active surface and an inactive surface which faces the active surface, a device isolation layer and a pad stacked on the active surface; and a through electrode disposed in a first via hole and a second via hole and including a protruding part that protrudes from the pad, the first via hole penetrating the semiconductor substrate, the second via hole penetrating the device insulation layer and the pad continuously, wherein at least a surface of the protruding part of the through electrode is formed of an oxidation resistance-conductive material.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件包括：半导体衬底，其包括活性表面和面向有源表面的无活性表面;器件隔离层和堆叠在有源表面上的焊盘; 以及设置在第一通孔中的贯通电极和第二通孔，并且包括从所述焊盘突出的突出部分，所述第一通孔贯穿所述半导体基板，所述第二通孔贯穿所述器件绝缘层和所述焊盘，其中， 贯通电极的突出部分的至少一个表面由抗氧化传导材料形成。

公开(公告)号：US20080179727A1

公开(公告)日：2008-07-31

申请号：US11852930

申请日：2007-09-10

申请人： Yong-Chai KWON ,  Keum-Hee MA ,  Dong-Ho LEE ,  Kang-Wook LEE

发明人： Yong-Chai KWON ,  Keum-Hee MA ,  Dong-Ho LEE ,  Kang-Wook LEE

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L25/50 ,  H01L23/147 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/24051 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14

摘要： Provided are semiconductor packages having immunity against a void due to an adhesive material and methods of fabricating the same. The semiconductor packages and the methods of fabricating the same can eliminate voids between package bodies to minimize delamination of the package bodies from the semiconductor package during the life time of semiconductor devices. To this end, a circuit substrate, a controller, and package bodies may be prepared. Each of the package bodies may have a package substrate, an adhesive pattern, and a package insulating layer. The package insulating layer may be formed on the package substrate to surround the adhesive pattern. The package bodies may be formed between the controller and the circuit substrate and contact the controller and the circuit substrate.

摘要翻译： 提供了由于粘合剂材料而具有对空隙的抗扰性的半导体封装及其制造方法。 半导体封装及其制造方法可以消除封装体之间的空隙，以在半导体器件的使用寿命期间最小化封装体与半导体封装的分层。 为此，可以制备电路基板，控制器和封装体。 每个封装体可以具有封装基板，粘合剂图案和封装绝缘层。 封装绝缘层可以形成在封装衬底上以包围粘合剂图案。 封装体可以形成在控制器和电路基板之间，并与控制器和电路基板接触。

公开(公告)号：US20090008790A1

公开(公告)日：2009-01-08

申请号：US12132925

申请日：2008-06-04

申请人： Ho-Jin LEE ,  Nam-Seog KIM ,  Yong-Chai KWON ,  Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG

发明人： Ho-Jin LEE ,  Nam-Seog KIM ,  Yong-Chai KWON ,  Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05561 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014

摘要： A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.

摘要翻译： 公开了一种具有通孔的半导体器件及其制造方法。 在一个实施例中，半导体器件包括形成在半导体衬底上的第一绝缘层。 具有用于露出第一绝缘层的一部分的第一孔的布线层形成在第一绝缘层上。 第二绝缘层形成在布线层的上部和第一孔中。 具有第二孔径以暴露第二绝缘层的一部分的导电焊盘形成在第二绝缘层上。 通过第一和第二绝缘层和半导体衬底的上部形成宽度比第一和第二孔的宽度窄的通孔。 在通孔中形成贯通电极。

公开(公告)号：US20080087974A1

公开(公告)日：2008-04-17

申请号：US11866940

申请日：2007-10-03

申请人： Yong-Chai KWON ,  Dong-Ho LEE

发明人： Yong-Chai KWON ,  Dong-Ho LEE

IPC分类号： H01L31/0232 ,  H01L31/18

CPC分类号： H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14685 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2924/12043 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a camera module and a method of fabricating the same. The method includes preparing a lens structure including upper connection portions. Lower connection portions are formed in a predetermined region of a substrate. The lower connection portions define a chip region and fit in the upper connection portions, respectively. An image sensor chip is located on the bottom surface of the chip region. The lens structure is adhered to the substrate using the upper and lower connection portions.

摘要翻译： 提供了一种相机模块及其制造方法。 该方法包括制备包括上连接部分的透镜结构。 下连接部分形成在基板的预定区域中。 下连接部分分别限定芯片区域并配合在上连接部分中。 图像传感器芯片位于芯片区域的底表面上。 透镜结构使用上连接部分和下连接部分粘合到基板上。

公开(公告)号：US20080179734A1

公开(公告)日：2008-07-31

申请号：US12018743

申请日：2008-01-23

申请人： Yong-Chai KWON ,  Dong-Ho LEE ,  Sun-Won KANG

发明人： Yong-Chai KWON ,  Dong-Ho LEE ,  Sun-Won KANG

IPC分类号： H01L23/538 ,  H01L21/52

CPC分类号： H01L25/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A stacked package includes a printed circuit board (PCB), a plurality of semiconductor chips, plugs and a controller. The semiconductor chips are sequentially stacked on the PCB. The plugs electrically connect each of the semiconductor chips to the PCB. The controller is disposed in any one of the semiconductor chips. The controller is electrically coupled to the plugs. Thus, the controller may be built in the semiconductor chip by a separate process so that a mechanical impact generated in a process for bonding the controller is not applied to the semiconductor chips. Further, a mechanical impact applied to the controller, which is generated in a process for forming a protection member, may be reduced.

摘要翻译： 堆叠式封装包括印刷电路板（PCB），多个半导体芯片，插头和控制器。 半导体芯片依次堆叠在PCB上。 插头将每个半导体芯片电连接到PCB。 控制器设置在任何一个半导体芯片中。 控制器电耦合到插头。 因此，可以通过单独的处理将控制器内置在半导体芯片中，使得在用于接合控制器的处理中产生的机械冲击不应用于半导体芯片。 此外，可以减少在形成保护构件的过程中产生的对控制器的机械冲击。

公开(公告)号：US20080088031A1

公开(公告)日：2008-04-17

申请号：US11866942

申请日：2007-10-03

申请人： Yong-Chai KWON ,  Dong-Ho LEE

发明人： Yong-Chai KWON ,  Dong-Ho LEE

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/13008 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor package structure and a method of fabricating the same are disclosed. A method of fabricating the semiconductor package structure can be characterized as including forming semiconductor chips on a semiconductor substrate. Each of the semiconductor chips includes chip pads. Through-vias are formed through the semiconductor chips. Redistribution structures and a chip selection interconnection layer are formed on the semiconductor chips, which connect the through-vias with the chip pads. The chip selection interconnection layers are patterned to form chip selection interconnection lines having different structures on at least one of the semiconductor chips. The semiconductor chips are stacked and electrically connected using the through-vias.

摘要翻译： 公开了一种半导体封装结构及其制造方法。 制造半导体封装结构的方法可以表征为包括在半导体衬底上形成半导体芯片。 每个半导体芯片包括芯片焊盘。 通孔通过半导体芯片形成。 重新分配结构和芯片选择互连层形成在将通孔与芯片焊盘连接的半导体芯片上。 芯片选择互连层被图案化以在至少一个半导体芯片上形成具有不同结构的芯片选择互连线。 半导体芯片使用贯通孔堆叠并电连接。