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    Semiconductor Memory Devices And Methods Of Fabricating The Same
    1.
    发明申请
    Semiconductor Memory Devices And Methods Of Fabricating The Same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US20120171837A1

    公开(公告)日：2012-07-05

    申请号：US13337999

    申请日：2011-12-27

    申请人： Youngkuk Kim ,  Insang Jeon ,  Youngseok Kim ,  Young-Lim Park ,  Ho-Kyun An

    发明人： Youngkuk Kim ,  Insang Jeon ,  Youngseok Kim ,  Young-Lim Park ,  Ho-Kyun An

    IPC分类号： H01L47/00

    CPC分类号： H01L45/12 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

    摘要： Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements.

    摘要翻译： 提供半导体存储器件及其制造方法。 该方法可以包括在多个第一沟槽的每一个中形成多个二极管图案，多个第一沟槽中的每一个包括至少两个有效区域，多个二极管图案占据多个空间，处理多个二极管图案 在所述多个空间中的每一个中形成多个半导体图案，去除所述多个半导体图案的部分以在所述多个空间中的每一个中形成凹部，处理所述多个半导体图案以形成多个二极管 多个空间中的每一个，在所述多个二极管中的每一个上形成底部电极，在每个所述底部电极上形成多个存储元件，并且在所述多个存储元件上形成多个上部互连线。

    Semiconductor memory devices and methods of fabricating the same
    2.
    发明授权
    Semiconductor memory devices and methods of fabricating the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US08652897B2

    公开(公告)日：2014-02-18

    申请号：US13337999

    申请日：2011-12-27

    申请人： Youngkuk Kim ,  Insang Jeon ,  Youngseok Kim ,  Young-Lim Park ,  Ho-Kyun An

    发明人： Youngkuk Kim ,  Insang Jeon ,  Youngseok Kim ,  Young-Lim Park ,  Ho-Kyun An

    IPC分类号： H01L21/8238

    CPC分类号： H01L45/12 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

    摘要： Provided are semiconductor memory devices and the methods of fabricating the same. The method may include forming a plurality of diode patterns in each of a plurality of first trenches, each of the plurality of first trenches including at least two active regions, the plurality of diode patterns occupying a plurality of spaces, treating the plurality of diode patterns to form a plurality of semiconductor patterns in each of the plurality of spaces, removing portions of the plurality of semiconductor patterns to form a recess in each of the plurality of spaces, treating the of the plurality of semiconductor patterns to form a plurality of diodes in each of the plurality of spaces, forming a bottom electrode on each of the plurality of diodes, forming a plurality of memory elements on each of the bottom electrodes, and forming a plurality of upper interconnection lines on the plurality of memory elements.

    摘要翻译： 提供半导体存储器件及其制造方法。 该方法可以包括在多个第一沟槽的每一个中形成多个二极管图案，多个第一沟槽中的每一个包括至少两个有效区域，多个二极管图案占据多个空间，处理多个二极管图案 在所述多个空间中的每一个中形成多个半导体图案，去除所述多个半导体图案的部分以在所述多个空间中的每一个中形成凹部，处理所述多个半导体图案以形成多个二极管 多个空间中的每一个，在所述多个二极管中的每一个上形成底部电极，在每个所述底部电极上形成多个存储元件，并且在所述多个存储元件上形成多个上部互连线。

    Method of forming a phase changeable material layer, a method of manufacturing a phase changeable memory unit, and a method of manufacturing a phase changeable semiconductor memory device
    3.
    发明授权
    Method of forming a phase changeable material layer, a method of manufacturing a phase changeable memory unit, and a method of manufacturing a phase changeable semiconductor memory device 有权
    形成相变材料层的方法，相变存储单元的制造方法以及相变半导体存储器件的制造方法

    公开(公告)号：US07569417B2

    公开(公告)日：2009-08-04

    申请号：US11353129

    申请日：2006-02-14

    申请人： Jin-Il Lee ,  Choong-Man Lee ,  Sung-Lae Cho ,  Young-Lim Park

    发明人： Jin-Il Lee ,  Choong-Man Lee ,  Sung-Lae Cho ,  Young-Lim Park

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1233 ,  C23C16/305 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

    摘要： A phase changeable material layer usable in a semiconductor memory device and a method of forming the same are disclosed. The method includes forming a plasma in a chamber having a substrate disposed therein, providing a first source gas including a germanium based material to form a first layer including the germanium based material on the substrate while maintaining the plasma in the chamber, providing a second source gas including a tellurium based material to react with the first layer to form a first composite material layer including a germanium-tellurium composite material on the substrate while maintaining the plasma in the chamber, providing a third source gas including an antimony based material to form a second layer including the antimony based material on the first composite material layer while maintaining the plasma in the chamber, and providing a fourth source gas including tellurium based material to react with the second layer including antimony based material to form a second composite material layer including an antimony-tellurium composite material on the first composite material layer. Accordingly, the phase changeable material layer may be formed at a low temperature and power to have desirable electrical characteristics.

    摘要翻译： 公开了可用于半导体存储器件的相变材料层及其形成方法。 该方法包括在具有设置在其中的基板的腔室中形成等离子体，提供包括锗基材料的第一源气体，以在将等离子体保持在腔室中的同时在基板上形成包括基于锗的材料的第一层，从而提供第二源 气体，其包括与第一层反应的碲基材料，以在衬底上形成包含锗 - 碲复合材料的第一复合材料层，同时将等离子体保持在室中，提供包括锑基材料的第三源气体，以形成 第二层，包括在第一复合材料层上的锑基材料，同时将等离子体保持在室中，并且提供包括碲基材料的第四源气体，以与包含锑基材料的第二层反应以形成第二复合材料层， 锑 - 碲复合材料在第一层复合材料上的铺设 r。 因此，可以在低温和功率下形成相变材料层以具有期望的电特性。

    METHOD OF FORMING SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20160118247A1

    公开(公告)日：2016-04-28

    申请号：US14920922

    申请日：2015-10-23

    申请人： Young-Lim Park ,  WONSEOK YOO ,  HYOKYOUNG KIM ,  CHANGYUP PARK ,  KONGSOO LEE ,  WOOK-YEOL YI ,  HANJIN LIM

    发明人： Young-Lim Park ,  WONSEOK YOO ,  HYOKYOUNG KIM ,  CHANGYUP PARK ,  KONGSOO LEE ,  WOOK-YEOL YI ,  HANJIN LIM

    IPC分类号： H01L21/02 ,  H01L21/311

    CPC分类号： H01L21/0217 ,  H01L21/02247 ,  H01L27/10885

    摘要： Provided is a method of forming a semiconductor device. The method can include loading a semiconductor substrate into semiconductor equipment. A base layer can be formed on the loaded semiconductor substrate by performing a base deposition process using a base source material. A first silicon layer can be formed on the base layer to a greater thickness than the base layer by performing a first silicon deposition process using a silicon source material different from the base source material. A first nitrided silicon layer can be formed by nitriding the first silicon layer using a first nitridation process. The semiconductor substrate having the first nitrided silicon layer can be unloaded from the semiconductor equipment.

    摘要翻译： 提供一种形成半导体器件的方法。 该方法可以包括将半导体衬底加载到半导体设备中。 可以通过使用基础源材料进行基底沉积工艺，在负载的半导体衬底上形成基底层。 可以通过使用不同于基础源材料的硅源材料进行第一硅沉积工艺，在基底层上形成比基底层更大的厚度的第一硅层。 可以通过使用第一氮化工艺氮化第一硅层来形成第一氮化硅层。 具有第一氮化硅层的半导体衬底可以从半导体设备卸载。

    Variable resistance memory device and methods of forming the same
    5.
    发明授权
    Variable resistance memory device and methods of forming the same 有权
    可变电阻存储器件及其形成方法

    公开(公告)号：US08558348B2

    公开(公告)日：2013-10-15

    申请号：US13584070

    申请日：2012-08-13

    申请人： Gyuhwan Oh ,  Dong-Hyun Im ,  Soonoh Park ,  Dongho Ahn ,  Young-Lim Park ,  Eun-Hee Cho

    发明人： Gyuhwan Oh ,  Dong-Hyun Im ,  Soonoh Park ,  Dongho Ahn ,  Young-Lim Park ,  Eun-Hee Cho

    IPC分类号： H01L21/8239 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11

    CPC分类号： H01L27/1052 ,  G11C13/0004 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

    摘要： A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.

    摘要翻译： 形成存储器件的方法包括在半导体衬底上形成第一层间绝缘层，在第一层间绝缘层中形成第一电极，第一电极具有在第一方向上延伸的矩形形状的顶表面，并形成 第一电极上的可变电阻图案，可变电阻图案具有沿与第一方向交叉的第二方向延伸的矩形形状的底表面，可变电阻图案的底表面与第一电极接触，其中， 下电极和可变电阻图案基本上等于第一电极的顶表面的短轴长度和可变电阻图案的底表面的短轴长度的乘积。

    Methods of forming a phase change memory device
    6.
    发明授权
    Methods of forming a phase change memory device 有权
    形成相变存储器件的方法

    公开(公告)号：US08187914B2

    公开(公告)日：2012-05-29

    申请号：US12731637

    申请日：2010-03-25

    申请人： Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Young-Lim Park ,  Jung-Hyeon Kim

    发明人： Jin-Il Lee ,  Urazaev Vladimir ,  Jin-Ha Jeong ,  Seung-Back Shin ,  Sung-Lae Cho ,  Hyeong-Geun An ,  Dong-Hyun Im ,  Young-Lim Park ,  Jung-Hyeon Kim

    IPC分类号： H01L21/20

    CPC分类号： H01L45/1616 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

    摘要： Provided are methods of forming a phase change memory device. A semiconductor device having a lower electrode and an interlayer insulating layer may be prepared. The lower electrode may be surrounded by the interlayer insulating layer. Source gases, a reaction gas and a purge gas may be injected into a process chamber of a semiconductor fabrication device to form a phase change material layer on a semiconductor substrate. The source gases may be simultaneously injected into the process chamber. The phase change material layer may be in contact with the lower electrode through the interlayer insulating layer. The phase change material layer may be etched to form a phase change memory cell in the interlayer insulating layer. An upper electrode may be formed on the phase change memory cell.

    摘要翻译： 提供形成相变存储器件的方法。 可以制备具有下电极和层间绝缘层的半导体器件。 下电极可以被层间绝缘层包围。 可以将源气体，反应气体和吹扫气体注入到半导体制造装置的处理室中，以在半导体衬底上形成相变材料层。 源气体可以同时注入到处理室中。 相变材料层可以通过层间绝缘层与下电极接触。 可以蚀刻相变材料层以在层间绝缘层中形成相变存储单元。 可以在相变存储单元上形成上电极。

    Methods of forming contact structures and semiconductor devices fabricated using contact structures
    7.
    发明授权
    Methods of forming contact structures and semiconductor devices fabricated using contact structures 有权
    形成接触结构的方法和使用接触结构制造的半导体器件

    公开(公告)号：US08021977B2

    公开(公告)日：2011-09-20

    申请号：US12627810

    申请日：2009-11-30

    申请人： Young-Lim Park ,  Hyeong-Geun An ,  Gyu-Hwan Oh ,  Dong-Ho Ahn ,  Jin-Il Lee

    发明人： Young-Lim Park ,  Hyeong-Geun An ,  Gyu-Hwan Oh ,  Dong-Ho Ahn ,  Jin-Il Lee

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76816 ,  H01L27/24

    摘要： Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sidewall of the first molding pattern, forming a second molding pattern to cover a sidewall of the insulating layer and spaced apart from the first molding pattern, removing a portion of the insulating layer between the first and second molding patterns to form a hole, and forming an insulating pattern between the first and second molding patterns, and forming a contact pattern in the hole.

    摘要翻译： 提供了形成使用接触结构制造的接触结构和半导体器件的方法。 接触结构的形成可以包括在基底上形成第一模制图案，形成绝缘层以覆盖至少第一模制图案的侧壁，形成第二模制图案以覆盖绝缘层的侧壁并与 第一模制图案，去除第一和第二模制图案之间的绝缘层的一部分以形成孔，并且在第一和第二模制图案之间形成绝缘图案，并在孔中形成接触图案。

    Phase change memory device including resistant material
    9.
    发明授权
    Phase change memory device including resistant material 失效
    相变记忆装置，包括耐磨材料

    公开(公告)号：US07759667B2

    公开(公告)日：2010-07-20

    申请号：US11762801

    申请日：2007-06-14

    申请人： Young-Lim Park ,  Sung-Lae Cho ,  Byoung-Jae Bae ,  Jin-il Lee ,  Hye-Young Park ,  Ji-Eun Lim

    发明人： Young-Lim Park ,  Sung-Lae Cho ,  Byoung-Jae Bae ,  Jin-il Lee ,  Hye-Young Park ,  Ji-Eun Lim

    IPC分类号： H01L29/04

    CPC分类号： H01L45/148 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

    摘要： A phase change memory device includes a lower electrode provided on a substrate, an interlayer insulating layer including a contact hole exposing the lower electrode, and covering the substrate, a resistant material pattern filling the contact hole, a phase change pattern interposed between the resistant material pattern and the interlayer insulating layer, and extending between the resistant material pattern and the lower electrode, wherein the resistant material pattern has a higher resistance than the phase change pattern, and an upper electrode in contact with the phase change pattern, the upper electrode being electrically connected to the lower electrode through the phase change pattern.

    摘要翻译： 相变存储器件包括设置在基板上的下电极，包括暴露下电极的接触孔并覆盖基板的层间绝缘层，填充接触孔的电阻材料图案，插入在电阻材料之间的相变图案 图案和层间绝缘层，并且在电阻材料图案和下电极之间延伸，其中电阻材料图案具有比相变图案更高的电阻，以及与相变图案接触的上电极，上电极为 通过相变图案电连接到下电极。