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    Image sensor chip package and method for forming the same
    1.
    发明授权
    Image sensor chip package and method for forming the same 有权
    图像传感器芯片封装及其形成方法

    公开(公告)号：US08692358B2

    公开(公告)日：2014-04-08

    申请号：US13217999

    申请日：2011-08-25

    申请人： Yu-Lung Huang ,  Tzu-Hsiang Hung ,  Yen-Shih Ho

    发明人： Yu-Lung Huang ,  Tzu-Hsiang Hung ,  Yen-Shih Ho

    IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L31/0232 ,  H01L29/22 ,  H01L23/538

    CPC分类号： H01L31/1876 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/13 ,  H01L2224/94

    摘要： A method for forming an image sensor chip package includes: providing a substrate having predetermined scribe lines defined thereon, wherein the predetermined scribe lines define device regions and each of the device regions has at least a device formed therein; disposing a support substrate on a first surface of the substrate; forming at least a spacer layer between the support substrate and the substrate, wherein the spacer layer covers the predetermined scribe lines; forming a package layer on a second surface of the substrate; forming conducting structures on the second surface of the substrate, wherein the conducting structures are electrically connected to the corresponding device in corresponding one of the device regions, respectively; and dicing along the predetermined scribe lines such that the support substrate is removed from the substrate and the substrate is separated into a plurality of individual image sensor chip packages.

    摘要翻译： 一种用于形成图像传感器芯片封装的方法，包括：提供具有限定在其上的预定划线的基板，其中，所述预定划线限定器件区域，并且每个器件区域至少具有形成在其中的器件; 将支撑基板设置在所述基板的第一表面上; 在所述支撑基板和所述基板之间形成至少间隔层，其中所述间隔层覆盖所述预定划线; 在所述基板的第二表面上形成封装层; 在所述衬底的第二表面上形成导电结构，其中所述导电结构分别在相应的一个所述器件区域中电连接到相应的器件; 并且沿着预定的划线切割，使得支撑基板从基板移除，并且基板被分离成多个单独的图像传感器芯片封装。

    Chip package
    2.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US08779452B2

    公开(公告)日：2014-07-15

    申请号：US13224267

    申请日：2011-09-01

    申请人： Tzu-Hsiang Hung ,  Hsin-Chih Chiu ,  Chuan-Jin Shiu ,  Chia-Sheng Lin ,  Yen-Shih Ho ,  Yu-Min Liang

    发明人： Tzu-Hsiang Hung ,  Hsin-Chih Chiu ,  Chuan-Jin Shiu ,  Chia-Sheng Lin ,  Yen-Shih Ho ,  Yu-Min Liang

    IPC分类号： H01L29/22

    CPC分类号： H01L27/14618 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2933/0066 ,  H01L2924/014 ,  H01L2924/00

    摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.

    摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在第一表面处的光电子器件; 保护层，设置在所述基板的第二表面上，其中所述保护层具有开口; 设置在所述基板的第二表面上并填充在所述开口中的导电凸块; 设置在所述保护层和所述基板之间的导电层，其中所述导电层将所述光电子器件电连接到所述导电凸块; 以及设置在保护层上的遮光层，其中遮光层不与导电凸块接触。

    Planar spiral inductor structure having enhanced Q value
    6.
    发明授权
    Planar spiral inductor structure having enhanced Q value 有权
    具有增强的Q值的平面螺旋电感器结构

    公开(公告)号：US07592891B2

    公开(公告)日：2009-09-22

    申请号：US12079059

    申请日：2008-03-24

    申请人： Hun-Ming Hsu ,  Yen-Shih Ho

    发明人： Hun-Ming Hsu ,  Yen-Shih Ho

    IPC分类号： H01F5/00

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/041 ,  H01F2017/0046 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49062 ,  Y10T29/49073 ,  H01L2924/00

    摘要： Within a method for fabricating an inductor structure there is first provided a substrate. There is then formed over the substrate a planar spiral conductor layer to form a planar spiral inductor, wherein a successive series of spirals within the planar spiral conductor layer is formed with a variation in at least one of: (1) a series of linewidths of the successive series of spirals; and (2) a series of spacings of the successive series of spirals. The method contemplates a planar spiral inductor structure fabricated in accord with the method. A planar spiral inductor structure fabricated in accord with the method is characterized by an enhanced Q value of the planar spiral inductor structure.

    摘要翻译： 在制造电感器结构的方法中，首先提供衬底。 然后在基板上形成平面螺旋导体层以形成平面螺旋形电感器，其中平面螺旋导体层内的连续的一系列螺旋形成为以下至少之一的变化：（1）一系列线宽 连续的一系列螺旋; 和（2）连续的螺旋系列的一系列间距。 该方法考虑了根据该方法制造的平面螺旋电感器结构。 根据该方法制造的平面螺旋电感器结构的特征在于平面螺旋电感器结构的增强的Q值。

    CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    8.
    发明申请
    CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
    芯片包装结构及其形成方法

    公开(公告)号：US20130020693A1

    公开(公告)日：2013-01-24

    申请号：US13548663

    申请日：2012-07-13

    申请人： Ho-Yin Yiu ,  Chien-Hung Liu ,  Tsang-Yu Liu ,  Ying-Nan Wen ,  Yen-Shih Ho

    发明人： Ho-Yin Yiu ,  Chien-Hung Liu ,  Tsang-Yu Liu ,  Ying-Nan Wen ,  Yen-Shih Ho

    IPC分类号： H01L29/02 ,  H01L21/50 ,  H01L21/02

    CPC分类号： B81B3/0051 ,  B81B2201/025 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.

    摘要翻译： 公开了一种用于形成芯片封装结构的芯片封装结构和方法。 至少一个块形成在盖的表面上，盖安装在其上形成有感测装置的基板上，用于覆盖感测装置，并且该块设置在盖和感测装置之间。 在本发明中，该块安装在盖上，不需要蚀刻盖以形成突出部分，因此本发明的方法简单且成本低。

    Method of fabricating a planar spiral inductor structure having an enhanced Q value
    9.
    发明授权
    Method of fabricating a planar spiral inductor structure having an enhanced Q value 有权
    制造具有增强的Q值的平面螺旋电感器结构的方法

    公开(公告)号：US07370403B1

    公开(公告)日：2008-05-13

    申请号：US09588788

    申请日：2000-06-06

    申请人： Hun-Ming Hsu ,  Yen-Shih Ho

    发明人： Hun-Ming Hsu ,  Yen-Shih Ho

    IPC分类号： H01F27/28 ,  G11B5/17

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/041 ,  H01F2017/0046 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49062 ,  Y10T29/49073 ,  H01L2924/00

    摘要： Within a method for fabricating an inductor structure there is first provided a substrate. There is then formed over the substrate a planar spiral conductor layer to form a planar spiral inductor, wherein a successive series of spirals within the planar spiral conductor layer is formed with a variation in at least one of: (1) a series of linewidths of the successive series of spirals; and (2) a series of spacings of the successive series of spirals. The method contemplates a planar spiral inductor structure fabricated in accord with the method. A planar spiral inductor structure fabricated in accord with the method is characterized by an enhanced Q value of the planar spiral inductor structure.

    摘要翻译： 在制造电感器结构的方法中，首先提供衬底。 然后在基板上形成平面螺旋导体层以形成平面螺旋形电感器，其中平面螺旋导体层内的连续的一系列螺旋形成为以下至少之一的变化：（1）一系列线宽 连续的一系列螺旋; 和（2）连续的螺旋系列的一系列间距。 该方法考虑了根据该方法制造的平面螺旋电感器结构。 根据该方法制造的平面螺旋电感器结构的特征在于平面螺旋电感器结构的增强的Q值。

    Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow
    10.
    发明授权
    Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow 有权
    铜工艺兼容CMOS金属 - 绝缘体 - 金属电容器结构及其工艺流程

    公开(公告)号：US06329234B1

    公开(公告)日：2001-12-11

    申请号：US09624026

    申请日：2000-07-24

    申请人： Ssu-Pin Ma ,  Chun-Hon Chen ,  Ta-Hsun Yeh ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou ,  Yen-Shih Ho

    发明人： Ssu-Pin Ma ,  Chun-Hon Chen ,  Ta-Hsun Yeh ,  Kuo-Reay Peng ,  Heng-Ming Hsu ,  Kong-Beng Thei ,  Chi-Wu Chou ,  Yen-Shih Ho

    IPC分类号： H01L218238

    CPC分类号： H01L28/40 ,  H01L21/3212 ,  H01L21/76838 ,  H01L28/56 ,  H01L28/60 ,  H01L28/90

    摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

    摘要翻译： 在许多混合信号或射频Rf应用中，同时需要电感器和电容器。 对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。 本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属​​电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用， 双镶嵌沟/通孔工艺。 本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。