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    Spacer elements for semiconductor device
    3.
    发明授权
    Spacer elements for semiconductor device 有权
    半导体器件的间隔元件

    公开(公告)号：US08455952B2

    公开(公告)日：2013-06-04

    申请号：US12951676

    申请日：2010-11-22

    申请人： Yun Jing Lin ,  Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang

    发明人： Yun Jing Lin ,  Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

    摘要： The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.

    摘要翻译： 本公开描述了一种包括半导体衬底和设置在半导体衬底上的栅极堆叠的半导体器件。 第一间隔元件设置在邻接第一栅极叠层的基板上。 在一个实施例中，第一间隔元件包括氮化硅。 第二间隔元件与第一间隔元件相邻。 在一个实施例中，第二间隔元件包括氧化硅。 凸起的源和第一升高的漏极被设置成横向接触第二间隔元件的侧壁。 在一个实施例中，触点与第二间隔元件直接接触。

    SPACER ELEMENTS FOR SEMICONDUCTOR DEVICE
    4.
    发明申请
    SPACER ELEMENTS FOR SEMICONDUCTOR DEVICE 有权
    半导体器件的间隔元件

    公开(公告)号：US20120126331A1

    公开(公告)日：2012-05-24

    申请号：US12951676

    申请日：2010-11-22

    申请人： Yun Jing Lin ,  Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang

    发明人： Yun Jing Lin ,  Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L29/772

    CPC分类号： H01L29/41783 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

    摘要： The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element.

    摘要翻译： 本公开描述了一种包括半导体衬底和设置在半导体衬底上的栅极堆叠的半导体器件。 第一间隔元件设置在邻接第一栅极叠层的基板上。 在一个实施例中，第一间隔元件包括氮化硅。 第二间隔元件与第一间隔元件相邻。 在一个实施例中，第二间隔元件包括氧化硅。 凸起的源和第一升高的漏极被设置成横向接触第二间隔元件的侧壁。 在一个实施例中，触点与第二间隔元件直接接触。

    Facet-free semiconductor device
    6.
    发明授权
    Facet-free semiconductor device 有权
    无方块半导体器件

    公开(公告)号：US08680625B2

    公开(公告)日：2014-03-25

    申请号：US12905579

    申请日：2010-10-15

    申请人： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

    发明人： Wei-Han Fan ,  Yu-Hsien Lin ,  Yimin Huang ,  Ming-Huan Tsai ,  Hsueh-Chang Sung ,  Chun-Fai Cheng

    IPC分类号： H01L27/088

    CPC分类号： H01L29/165 ,  H01L21/28123 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： An exemplary semiconductor device is described, which includes a semiconductor substrate having an active region and an isolation region. The active region has a first edge which interfaces with the isolation region. A gate structure formed on the semiconductor substrate. A spacer element abuts the gate structure and overlies the first edge. In an embodiment, the isolation region is an STI structure. An epitaxy region may be formed adjacent the spacer. In embodiments, this epitaxy region is facet-free.

    摘要翻译： 描述了一种示例性的半导体器件，其包括具有有源区和隔离区的半导体衬底。 有源区域具有与隔离区域相接合的第一边缘。 形成在半导体衬底上的栅极结构。 间隔元件邻接栅极结构并覆盖在第一边缘上。 在一个实施例中，隔离区域是STI结构。 可以在间隔物附近形成外延区域。 在实施例中，该外延区域是无面的。

    Poly resistor on a semiconductor device
    8.
    发明授权
    Poly resistor on a semiconductor device 有权
    半导体器件上的聚电阻

    公开(公告)号：US08058125B1

    公开(公告)日：2011-11-15

    申请号：US12850390

    申请日：2010-08-04

    申请人： Yu-Hsien Lin ,  Inez Fu ,  Yimin Huang

    发明人： Yu-Hsien Lin ,  Inez Fu ,  Yimin Huang

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/0629

    摘要： The present disclosure provides a poly resistor on a semiconductor device and a method of fabricating the same. In an embodiment, a poly silicon resistor device is formed by providing a substrate having a first region and a second region. A dummy gate stack is formed on the substrate in the first region, wherein the dummy gate stack has a dummy gate stack thickness extending above the substrate. A poly silicon resister is formed on the substrate in the second region, wherein the poly silicon resistor has a poly silicon resistor thickness extending above the substrate a distance which is less than the dummy gate stack thickness. A dopant is implanted into the substrate in the first region thereby forming a source region and a drain region in the first region of the substrate. The dopant is also implanted into the poly silicon resistor. An inter-level dielectric (ILD) layer is formed on the substrate over the dummy gate stack and also over the poly silicon resistor. The ILD layer is planarized, thereby exposing the dummy gate stack and leaving a portion of the ILD layer over the poly silicon resistor. The dummy gate stack is replaced with a high k metal gate while using the portion of the ILD layer over the poly silicon resistor as a mask to protect the poly silicon resistor during replacement of the dummy gate stack with the high k metal gate.

    摘要翻译： 本公开在半导体器件上提供多晶硅电阻器及其制造方法。 在一个实施例中，通过提供具有第一区域和第二区域的衬底来形成多晶硅电阻器件。 在第一区域中的基板上形成虚拟栅极堆叠，其中虚拟栅极堆叠具有在基板上方延伸的虚拟栅极叠层厚度。 在第二区域中的基板上形成多晶硅电阻器，其中多晶硅电阻器具有在基板上方延伸的距离小于虚拟栅极叠层厚度的多晶硅电阻器厚度。 掺杂剂注入到第一区域中的衬底中，从而在衬底的第一区域中形成源极区域和漏极区域。 掺杂剂也被注入到多晶硅电阻器中。 在虚拟栅极堆叠上并且还在多晶硅电阻器上方的衬底上形成层间电介质（ILD）层。 ILD层被平坦化，从而暴露虚拟栅极堆叠并将ILD层的一部分留在多晶硅电阻上。 在使用多晶硅电阻器上的ILD层的部分作为掩模的情况下，用高k金属栅极替代伪栅极堆叠，以在用高k金属栅极替换伪栅极堆叠期间保护多晶硅电阻器。

    Method of forming dual damascene structure
    10.
    发明授权
    Method of forming dual damascene structure 有权

    公开(公告)号：US06593223B1

    公开(公告)日：2003-07-15

    申请号：US09524720

    申请日：2000-03-14

    申请人： Yimin Huang ,  Tri-Rung Yew

    发明人： Yimin Huang ,  Tri-Rung Yew

    IPC分类号： H01L214763

    CPC分类号： H01L21/76829 ,  H01L21/76807

    摘要： A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.