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19 条记录 (耗时 0.038 秒)

    Method of fabrication of a semiconductor apparatus comprising substrates including Al/Ge and Cu contact layers to form a metallic alloy
    4.
    发明授权
    Method of fabrication of a semiconductor apparatus comprising substrates including Al/Ge and Cu contact layers to form a metallic alloy 有权
    制造包括Al / Ge和Cu接触层的基板以形成金属合金的半导体装置的制造方法

    公开(公告)号：US08741738B2

    公开(公告)日：2014-06-03

    申请号：US13156052

    申请日：2011-06-08

    申请人： Yi Hsun Chiu ,  Ting-Ying Chien ,  Ching-Hou Su ,  Chyi-Tsong Ni

    发明人： Yi Hsun Chiu ,  Ting-Ying Chien ,  Ching-Hou Su ,  Chyi-Tsong Ni

    IPC分类号： H01L21/30

    CPC分类号： B81C1/00269 ,  B81B2207/07 ,  B81C2203/035

    摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.

    摘要翻译： 本公开涉及集成电路制造，更具体地涉及具有金属合金的半导体器件。 用于装置的示例性结构包括第一硅衬底; 第二硅衬底; 以及连接所述第一和第二基板中的每一个的触点，其中所述触点包括邻近所述第一硅衬底的Ge层，与所述第二硅衬底相邻的Cu层，以及所述Ge层和所述Cu层之间的金属合金。

    METHOD AND APPARATUS FOR SEMICONDUCTOR WAFER
    7.
    发明公开
    METHOD AND APPARATUS FOR SEMICONDUCTOR WAFER 审中-公开

    公开(公告)号：US20240001409A1

    公开(公告)日：2024-01-04

    申请号：US18226495

    申请日：2023-07-26

    申请人： Kuang-Wei Cheng ,  Cheng-Lung Wu ,  Chyi-Tsong Ni

    发明人： Kuang-Wei Cheng ,  Cheng-Lung Wu ,  Chyi-Tsong Ni

    IPC分类号： B08B3/02 ,  B08B3/04

    CPC分类号： B08B3/02 ,  B08B3/04 ,  B08B2240/00

    摘要： A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.

    Low temperature method for minimizing copper hillock defects
    8.
    发明授权
    Low temperature method for minimizing copper hillock defects 有权
    用于最小化铜小丘缺陷的低温方法

    公开(公告)号：US07851358B2

    公开(公告)日：2010-12-14

    申请号：US11122393

    申请日：2005-05-05

    申请人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

    发明人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/76801 ,  H01L21/76883

    摘要： A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

    摘要翻译： 公开了一种在衬底上制造铜互连的方法，其中互连和衬底在互连的极化之后并且在沉积上覆的电介质层之前经受低温退火。 低温退火在随后的介电层的高温沉积期间抑制铜材料中的小丘的形成。 小丘可以突出穿过钝化层，从而在形成在衬底上的半导体器件的连接之内引起短路。 在一个实例中，在包含氢气（5份/百份）和氮气（95份/百份）的形成气体环境中，在大约200℃的温度下将互连和衬底退火约180秒的时间。

    Method to produce porous oxide including forming a precoating oxide and a thermal oxide
    9.
    发明授权
    Method to produce porous oxide including forming a precoating oxide and a thermal oxide 失效
    包括形成预涂氧化物和热氧化物的多孔氧化物的方法

    公开(公告)号：US06777347B1

    公开(公告)日：2004-08-17

    申请号：US09765044

    申请日：2001-01-19

    申请人： Chyi-Tsong Ni ,  Eric Su

    发明人： Chyi-Tsong Ni ,  Eric Su

    IPC分类号： H01L2131

    CPC分类号： H01L21/02126 ,  C23C16/402 ,  C23C16/4404 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/31695

    摘要： A method for forming porous silicon oxide film, comprising the following steps. A CVD chamber having inner walls and a wafer chuck/heater is provided. At least a portion of the CVD chamber inner walls is pre-coated with a layer of first PECVD silicon oxide film having a first thermal CVD oxide deposition rate thereupon. A semiconductor wafer is placed on the wafer chuck/heater within pre-coated CVD chamber. The semiconductor wafer including an upper second PECVD silicon oxide film having a second thermal CVD oxide deposition rate thereupon that is less than the first thermal CVD oxide deposition rate upon the first PECVD silicon oxide film coating the CVD chamber inner walls. A porous silicon oxide film is deposited upon the upper second PECVD silicon oxide film overlying the semiconductor wafer. The porous silicon oxide film being different from the first PECVD silicon oxide film coating the CVD chamber inner walls.

    摘要翻译： 一种形成多孔氧化硅膜的方法，包括以下步骤。 提供具有内壁和晶片卡盘/加热器的CVD室。 CVD室内壁的至少一部分预先涂覆有在其上具有第一热CVD氧化物沉积速率的第一PECVD氧化硅膜层。 将半导体晶片放置在预涂CVD室内的晶片卡盘/加热器上。 该半导体晶片包括具有第二热CVD氧化物沉积速率的上部第二PECVD氧化硅膜，该第二热CVD氧化物沉积速率小于在CVD室内壁上涂覆第一PECVD氧化硅膜时的第一热CVD氧化物沉积速率。 多孔氧化硅膜沉积在覆盖半导体晶片的上部第二PECVD氧化硅膜上。 多孔氧化硅膜与涂覆CVD室内壁的第一PECVD氧化硅膜不同。

    Passivation layer for semiconductor devices
    10.
    发明授权
    Passivation layer for semiconductor devices 有权
    半导体器件钝化层

    公开(公告)号：US08643151B2

    公开(公告)日：2014-02-04

    申请号：US13036897

    申请日：2011-02-28

    申请人： Jen-Hao Liu ,  Chyi-Tsong Ni ,  Hsiao-Yin Lin ,  Chung-Min Lin

    发明人： Jen-Hao Liu ,  Chyi-Tsong Ni ,  Hsiao-Yin Lin ,  Chung-Min Lin

    IPC分类号： H01L23/58

    CPC分类号： H01L23/3192 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T1 and being separated by a gap. A composite passivation layer comprises a HDP CVD oxide layer under a nitride layer. The composite passivation layer is disposed over the metal features and partially fills the gap. The composite passivation layer has a thickness T2 about 20% to 50% of the thickness T1.

    摘要翻译： 本公开的实施例提供一种半导体器件。 半导体器件包括多个金属化层，其包括最上面的金属化层。 最上面的金属化层具有两个具有厚度T1并被间隙隔开的金属特征。 复合钝化层包括氮化物层下的HDP CVD氧化物层。 复合钝化层设置在金属特征上并部分填充间隙。 复合钝化层的厚度T2约为厚度T1的20％至50％。