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21 条记录 (耗时 0.022 秒)

    STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS
    5.
    发明申请
    STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS 失效
    在半导体器件中的STI形成，包括SOI和块状硅区域

    公开(公告)号：US20050282392A1

    公开(公告)日：2005-12-22

    申请号：US10710060

    申请日：2004-06-16

    申请人： Michael Steigerwalt ,  Mahender Kumar ,  Herbert Ho ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Denise Pendleton

    发明人： Michael Steigerwalt ,  Mahender Kumar ,  Herbert Ho ,  David Dobuzinsky ,  Johnathan Faltermeier ,  Denise Pendleton

    IPC分类号： H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762

    CPC分类号： H01L21/7624 ,  H01L21/3081 ,  H01L21/31612 ,  H01L21/76283

    摘要： Methods for forming or etching silicon trench isolation (STI) in a silicon-on-insulator (SOI) region and a bulk silicon region, and a semiconductor device so formed, are disclosed. The STI can be etched simultaneously in the SOI and bulk silicon regions by etching to an uppermost silicon layer using an STI mask, conducting a timed etch that etches to a desired depth in the bulk silicon region and stops on a buried insulator of the SOI region, and etching through the buried insulator of the SOI region. The buried insulator etch for this process can be done with little complexity as part of a hardmask removal step. Further, by choosing the same depth for both the bulk and SOI regions, problems with a subsequent CMP process are avoided. The invention also cleans up the boundary between the SOI and bulk regions where silicon nitride residuals may exist.

    摘要翻译： 公开了在绝缘体上硅（SOI）区域和体硅区域中形成或蚀刻硅沟槽隔离（STI）的方法以及如此形成的半导体器件。 可以通过使用STI掩模蚀刻到最上层的硅层，在SOI和体硅区域中同时蚀刻STI，进行蚀刻到体硅区域中期望的深度并停止在SOI区域的埋入绝缘体上的定时蚀刻 ，并蚀刻穿过SOI区域的埋层绝缘体。 用于该过程的掩埋绝缘体蚀刻可以以很少的复杂性作为硬掩模去除步骤的一部分来完成。 此外，通过为体区和SOI区域选择相同的深度，避免了后续CMP工艺的问题。 本发明还清除了可能存在氮化硅残留的SOI和体区之间的边界。

    Pitcher-shaped active area for field effect transistor and method of forming same
    6.
    发明授权
    Pitcher-shaped active area for field effect transistor and method of forming same 失效
    投币型场效应晶体管及其形成方法

    公开(公告)号：US06960514B2

    公开(公告)日：2005-11-01

    申请号：US10803395

    申请日：2004-03-18

    申请人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    发明人： Jochen Beintner ,  Rama Divakaruni ,  Johnathan Faltermeier ,  Philip L. Flaitz ,  Oleg Gluschenkov ,  Carol J. Heenan ,  Rajarao Jammy ,  Byeong Kim ,  Mihel Seitz ,  Akira Sudo ,  Yoichi Takegawa

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224

    摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

    摘要翻译： 对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。 投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。 还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部 区域结构。 本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

    SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS
    7.
    发明申请
    SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS 失效
    自定义阵列与记忆体的联系

    公开(公告)号：US20050077562A1

    公开(公告)日：2005-04-14

    申请号：US10605590

    申请日：2003-10-10

    申请人： Rama Divakaruni ,  Johnathan Faltermeier ,  Michael Maldei ,  Jay Strane

    发明人： Rama Divakaruni ,  Johnathan Faltermeier ,  Michael Maldei ,  Jay Strane

    IPC分类号： H01L21/60 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76897 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

    摘要： A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

    摘要翻译： 提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。 该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。 在槽中形成与基板和位线的位线接触。 此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管 在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

    Semi-insulating diffusion barrier for low-resistivity gate conductors
    8.
    发明授权
    Semi-insulating diffusion barrier for low-resistivity gate conductors 失效
    用于低电阻率栅极导体的半绝缘扩散阻挡层

    公开(公告)号：US06444516B1

    公开(公告)日：2002-09-03

    申请号：US09613197

    申请日：2000-07-07

    申请人： Lawrence Alfred Clevenger ,  Jack A. Mandelman ,  Rajarao Jammy ,  Oleg Gluschenkov ,  Irene Lennox McStay ,  Kwong Hon Wong ,  Johnathan Faltermeier

    发明人： Lawrence Alfred Clevenger ,  Jack A. Mandelman ,  Rajarao Jammy ,  Oleg Gluschenkov ,  Irene Lennox McStay ,  Kwong Hon Wong ,  Johnathan Faltermeier

    IPC分类号： H01L218234

    CPC分类号： H01L21/28044 ,  H01L29/4941

    摘要： A gate structure for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer on a semiconductor substrate, over which a polysilicon gate electrode is formed. The gate structure further includes a gate conductor that is electrically connected with the gate electrode through a diffusion barrier layer having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.

    摘要翻译： 用于半导体器件的栅极结构，特别是用于诸如CMOS技术的应用的MOSFET。 栅结构需要在半导体衬底上形成电绝缘层，形成多晶硅栅电极。 栅极结构还包括通过具有半绝缘性质的扩散阻挡层与栅电极电连接的栅极导体。 调整扩散阻挡层的组成和厚度，使得阻挡层有效地阻挡栅极导体和多晶硅栅电极之间的扩散和混合，但提供足够的电容耦合和/或电流泄漏，从而不显着增加栅极 门结构的传播延迟。

    Trench memory with self-aligned strap formed by self-limiting process
    9.
    发明授权
    Trench memory with self-aligned strap formed by self-limiting process 失效
    沟槽记忆带自行排列的带子，由自限制过程形成

    公开(公告)号：US07749835B2

    公开(公告)日：2010-07-06

    申请号：US12048263

    申请日：2008-03-14

    申请人： Xi Li ,  Kangguo Cheng ,  Johnathan Faltermeier

    发明人： Xi Li ,  Kangguo Cheng ,  Johnathan Faltermeier

    IPC分类号： H01L21/84 ,  H01L21/8242

    CPC分类号： H01L29/945 ,  H01L21/32137 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1087 ,  H01L29/66181

    摘要： A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

    摘要翻译： 描述半导体结构。 该结构包括形成在具有绝缘体上半导体（SOI）层和掩埋绝缘（BOX）层的半导体衬底中的沟槽开口; 以及形成在所述沟槽开口中的填充材料，所述填充材料在所述沟槽存储单元内形成“V”形，其中所述“V”形包括基本上邻近所述BOX层的顶表面的顶部。 还描述了制造半导体结构的方法。 该方法包括在具有SOI层和BOX层的半导体衬底中形成沟槽开口; 横向蚀刻BOX层，使得与BOX层相关联的沟槽开口的一部分基本上大于与SOI层相关联的沟槽开口的一部分; 用填充材料填充沟槽开口; 并使填充材料凹陷。

    POLYSILICON HARD MASK FOR ENHANCED ALIGNMENT SIGNAL
    10.
    发明申请
    POLYSILICON HARD MASK FOR ENHANCED ALIGNMENT SIGNAL 失效

    公开(公告)号：US20070262475A1

    公开(公告)日：2007-11-15

    申请号：US11382540

    申请日：2006-05-10

    申请人： Kangguo Cheng ,  Johnathan Faltermeier ,  James Norum

    发明人： Kangguo Cheng ,  Johnathan Faltermeier ,  James Norum

    IPC分类号： H01L23/544

    CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/321 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

    摘要： A method is provided for forming a polysilicon layer on a substrate and aligning an exposure system with an alignment feature of the substrate through the polysilicon layer. In such method, a polysilicon layer is deposited over the substrate having the alignment feature such that the polysilicon layer reaches a first temperature. The polysilicon layer is then annealed with the substrate to raise the polysilicon layer to a second temperature higher than the first temperature. A photoimageable layer is then deposited over the polysilicon layer, after which an alignment signal including light from the alignment feature is received through the annealed polysilicon layer. Using the alignment signal passing through the annealed polysilicon layer from the alignment feature, an exposure system is aligned with the substrate with improved results.

    摘要翻译： 提供了一种在衬底上形成多晶硅层并且通过多晶硅层将曝光系统与衬底的对准特征对准的方法。 在这种方法中，多晶硅层沉积在具有对准特征的衬底上，使得多晶硅层达到第一温度。 然后将多晶硅层与衬底退火以将多晶硅层升高到高于第一温度的第二温度。 然后在多晶硅层上沉积可光成像层，之后通过退火的多晶硅层接收包括来自对准特征的光的对准信号。 使用通过来自对准特征的退火多晶硅层的对准信号，曝光系统与衬底对准，并具有改进的结果。