公开(公告)号：US09059067B2

公开(公告)日：2015-06-16

申请号：US13235546

申请日：2011-09-19

申请人： Yun-seok Choi ,  So-young Lim ,  In-won O

发明人： Yun-seok Choi ,  So-young Lim ,  In-won O

IPC分类号： H01L29/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/147 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/0401

摘要： A semiconductor device includes an interposer mounting a semiconductor chip. The interposer includes a silicon substrate having a recessed region formed on a first surface, a first through via penetrating a first region of the silicon substrate from the first surface to an opposing second surface, an insulator disposed in the recessed region, and a first wire pattern at least partially disposed on the insulator and electrically connecting the first through via to the semiconductor chip.

摘要翻译： 半导体器件包括安装半导体芯片的插入器。 插入器包括硅基板，其具有形成在第一表面上的凹陷区域，穿过硅基板的第一区域的第一通孔从第一表面到相对的第二表面，设置在凹陷区域中的绝缘体和第一引线 至少部分地设置在所述绝缘体上并将所述第一通孔电连接到所述半导体芯片。

公开(公告)号：US20120091468A1

公开(公告)日：2012-04-19

申请号：US13235546

申请日：2011-09-19

申请人： Yun-seok Choi ,  So-young Lim ,  In-won O

发明人： Yun-seok Choi ,  So-young Lim ,  In-won O

IPC分类号： H01L23/48 ,  H01L29/24

CPC分类号： H01L23/147 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/0401

摘要： A semiconductor device includes an interposer mounting a semiconductor chip. The interposer includes a silicon substrate having a recessed region formed on a first surface, a first through via penetrating a first region of the silicon substrate from the first surface to an opposing second surface, an insulator disposed in the recessed region, and a first wire pattern at least partially disposed on the insulator and electrically connecting the first through via to the semiconductor chip

摘要翻译： 半导体器件包括安装半导体芯片的插入器。 插入器包括硅基板，其具有形成在第一表面上的凹陷区域，穿过硅基板的第一区域的第一通孔从第一表面到相对的第二表面，设置在凹陷区域中的绝缘体和第一引线 至少部分地设置在所述绝缘体上并将所述第一通孔电连接到所述半导体芯片

公开(公告)号：US20120068349A1

公开(公告)日：2012-03-22

申请号：US13223624

申请日：2011-09-01

申请人： Dong-han Kim ,  So-young Lim

发明人： Dong-han Kim ,  So-young Lim

IPC分类号： H01L23/52

CPC分类号： H01L23/4985 ,  H01L23/49838 ,  H01L24/06 ,  H01L2224/0603 ,  H01L2224/06155 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/351 ,  H01L2924/00

摘要： A tape package providing a plurality of input and output portions each having a minimum pitch. The tape package includes a tape wiring substrate including first and second wirings, and a semiconductor chip mounted on the tape wiring substrate, and including a first edge, a first pad disposed adjacent to the first edge, and a second pad disposed to be farther spaced apart from the first edge than the first pad, where the first wiring is connected to a portion of the first pad that is spaced from the first edge by a first distance, and where the second wiring is connected to a portion of the second pad that is spaced from the first edge by a second distance that is greater than the first distance.

摘要翻译： 一种提供多个具有最小间距的输入和输出部分的磁带封装。 所述带包装包括包括第一和第二布线的带布线基板，以及安装在所述带布线基板上的半导体芯片，并且包括第一边缘，邻近所述第一边缘设置的第一焊盘和设置成更远的间隔的第二焊盘 除了第一边缘之外，第一布线连接到第一焊盘的与第一边缘间隔开第一距离的部分，并且其中第二布线连接到第二焊盘的一部分， 与第一边缘间隔开大于第一距离的第二距离。

公开(公告)号：US07760044B2

公开(公告)日：2010-07-20

申请号：US11761416

申请日：2007-06-12

申请人： Eun-seok Song ,  Hee-seok Lee ,  So-young Lim

发明人： Eun-seok Song ,  Hee-seok Lee ,  So-young Lim

IPC分类号： H04B3/28

CPC分类号： H01Q15/006

摘要： A substrate for a semiconductor package comprises a dielectric substrate, a circuit pattern, and an electromagnetic band gap (EBG) pattern. The circuit pattern is formed on a first surface of the dielectric substrate and is connected to ground via a ground connection. The electromagnetic band gap (EBG) pattern comprises a plurality of zigzag unit structures formed on a second surface of the dielectric substrate, wherein the second surface is formed on an opposite side of the dielectric substrate from the first surface; the zigzag unit structures are electrically connected to each other; and at least one of the zigzag unit structures is electrically connected to the ground connection.

摘要翻译： 用于半导体封装的衬底包括电介质衬底，电路图案和电磁带隙（EBG）图案。 电路图案形成在电介质基板的第一表面上，并通过接地连接接地。 电磁带隙（EBG）图案包括形成在电介质基板的第二表面上的多个之字形单元结构，其中第二表面形成在电介质基板的与第一表面相反的一侧上; 之字形单元结构彼此电连接; 并且所述之字形单元结构中的至少一个电连接到所述接地连接。

公开(公告)号：US07936232B2

公开(公告)日：2011-05-03

申请号：US12824415

申请日：2010-06-28

申请人： Eun-seok Song ,  Hee-seok Lee ,  So-young Lim

发明人： Eun-seok Song ,  Hee-seok Lee ,  So-young Lim

IPC分类号： H04B3/28

CPC分类号： H01Q15/006

摘要： A substrate for a semiconductor package includes a dielectric substrate, a circuit pattern formed on a first surface of the dielectric substrate, and an electromagnetic band gap (EGB) pattern. The EGB pattern includes multiple unit structures formed on a second surface of the dielectric substrate, where each unit structure includes a flat conductor electrically connected to the circuit pattern through a ground connection, and multiple spiral-patterned conductors electrically connected to the flat conductor. The second surface is formed on an opposite side of the dielectric substrate from the first surface. Each flat conductor is electrically connected to a flat conductor of another one of the unit structures. At least one of the spiral-patterned conductors in each one of the unit structures is electrically connected to another one of the spiral-patterned conductors.

摘要翻译： 用于半导体封装的衬底包括电介质衬底，形成在电介质衬底的第一表面上的电路图案和电磁带隙（EGB）图案。 EGB图案包括形成在电介质基板的第二表面上的多个单元结构，其中每个单元结构包括通过接地连接电连接到电路图案的扁平导体，以及电连接到扁平导体的多个螺旋图案导体。 第二表面形成在电介质基板的与第一表面相反的一侧上。 每个扁平导体电连接到另一个单元结构的扁平导体。 每个单元结构中的至少一个螺旋图案导体电连接到另一个螺旋图案导体。

公开(公告)号：US20100276189A1

公开(公告)日：2010-11-04

申请号：US12772385

申请日：2010-05-03

申请人： Eun seok Song ,  Hee seok Lee ,  Hyun-a Kim ,  So-young Lim

发明人： Eun seok Song ,  Hee seok Lee ,  Hyun-a Kim ,  So-young Lim

IPC分类号： H05K1/18 ,  H05K1/11

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48233 ,  H01L2224/48235 ,  H01L2224/48237 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

摘要翻译： 在具有相对于衬底在水平和垂直方向上延伸的存储器单元阵列的三维存储器件的多位编程的方法中，该方法包括首先将要编程的存储器单元编程为第一组 状态。 然后，首先对与第一组状态中的一个相邻的要存储单元相邻的至少一个相邻存储单元进行编程。 在对所述至少一个相邻存储器单元进行第一编程之后，将要编程的存储器单元的第二编程为第二组状态之一，其中所述第二组状态具有大于所述状态数 第一套状态。

公开(公告)号：US08581373B2

公开(公告)日：2013-11-12

申请号：US13223624

申请日：2011-09-01

申请人： Dong-han Kim ,  So-young Lim

发明人： Dong-han Kim ,  So-young Lim

IPC分类号： H01L23/495 ,  H01L23/053

CPC分类号： H01L23/4985 ,  H01L23/49838 ,  H01L24/06 ,  H01L2224/0603 ,  H01L2224/06155 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/351 ,  H01L2924/00

摘要： A tape package providing a plurality of input and output portions each having a minimum pitch. The tape package includes a tape wiring substrate including first and second wirings, and a semiconductor chip mounted on the tape wiring substrate, and including a first edge, a first pad disposed adjacent to the first edge, and a second pad disposed to be farther spaced apart from the first edge than the first pad, where the first wiring is connected to a portion of the first pad that is spaced from the first edge by a first distance, and where the second wiring is connected to a portion of the second pad that is spaced from the first edge by a second distance that is greater than the first distance.

摘要翻译： 一种提供多个具有最小间距的输入和输出部分的磁带封装。 所述带包装包括包括第一和第二布线的带布线基板，以及安装在所述带布线基板上的半导体芯片，并且包括第一边缘，邻近所述第一边缘设置的第一焊盘和设置成更远的间隔的第二焊盘 除了第一边缘之外，第一布线连接到第一焊盘的与第一边缘间隔开第一距离的部分，并且其中第二布线连接到第二焊盘的一部分， 与第一边缘间隔开大于第一距离的第二距离。

公开(公告)号：US08502084B2

公开(公告)日：2013-08-06

申请号：US12772385

申请日：2010-05-03

申请人： Eun seok Song ,  Hee seok Lee ,  Hyun-a Kim ,  So-young Lim

发明人： Eun seok Song ,  Hee seok Lee ,  Hyun-a Kim ,  So-young Lim

IPC分类号： H05K1/11

CPC分类号： H01L23/50 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48233 ,  H01L2224/48235 ,  H01L2224/48237 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor chip carrier having multiple conductive layers separated from each other by dielectric layers, a chip bonding position at an intermediate portion of a top surface of the semiconductor chip carrier, and a bonding region spaced apart from the chip bonding position. The bonding region includes a first bonding region closest to the chip bonding position, a second bonding region most distant from the chip bonding position, and a third bonding region positioned between the first bonding region and the second bonding region. The first bonding region, the second bonding region and the third bonding region are electrically insulated from each other and the first bonding region is configured to carry a first voltage, the second bonding region is configured to carry a second voltage and the third bonding region is configured to carry a third voltage that is less than the first voltage and less than the second voltage.

摘要翻译： 一种半导体芯片载体，其具有通过电介质层彼此分离的多个导电层，在半导体芯片载体的上表面的中间部分处的芯片接合位置以及与芯片接合位置间隔开的接合区域。 接合区域包括最靠近芯片接合位置的第一接合区域，最靠近芯片接合位置的第二接合区域和位于第一接合区域和第二接合区域之间的第三接合区域。 第一接合区域，第二接合区域和第三接合区域彼此电绝缘，并且第一接合区域被配置为承载第一电压，第二接合区域被配置为承载第二电压，并且第三接合区域是 被配置为承载小于所述第一电压并小于所述第二电压的第三电压。