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公开(公告)号:US07986037B2
公开(公告)日:2011-07-26
申请号:US12068606
申请日:2008-02-08
申请人: Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
发明人: Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
IPC分类号: H01L23/52
CPC分类号: H05K1/0231 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L2224/16225 , H01L2924/12044 , H01L2924/3011 , H05K1/09 , H05K1/111 , H05K1/167 , H05K2201/0352 , H05K2201/0391 , H05K2201/09236 , H05K2201/09309 , H05K2201/09481 , H05K2201/09781 , H05K2201/10636 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
摘要翻译: 作为半导体芯片中的馈电路径,可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径,从而抑制半导体器件的功率噪声。 通过插入将中频带中的电阻提升到电阻本身较高的部分的结构,例如半导体封装中的功率布线和电容器互连电极部件,可以有效地减少中频带中的反谐振阻抗,同时保持 阻抗低在低频。
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公开(公告)号:US20080290495A1
公开(公告)日:2008-11-27
申请号:US12068606
申请日:2008-02-08
申请人: Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
发明人: Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
IPC分类号: H01L23/528
CPC分类号: H05K1/0231 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L2224/16225 , H01L2924/12044 , H01L2924/3011 , H05K1/09 , H05K1/111 , H05K1/167 , H05K2201/0352 , H05K2201/0391 , H05K2201/09236 , H05K2201/09309 , H05K2201/09481 , H05K2201/09781 , H05K2201/10636 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
摘要翻译: 作为半导体芯片中的馈电路径,可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径,从而抑制半导体器件的功率噪声。 通过插入将中频带中的电阻提升到电阻本身较高的部分的结构,例如半导体封装中的功率布线和电容器互连电极部件,可以有效地减少中频带中的反谐振阻抗,同时保持 阻抗低在低频。
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3.
公开(公告)号:US20100309706A1
公开(公告)日:2010-12-09
申请号:US12801326
申请日:2010-06-03
申请人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
CPC分类号: G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译: 存储器模块包括多个存储器芯片,多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。 数据寄存器缓冲器与存储器芯片执行数据传输。 命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。 缓冲的命令/地址/控制信号被提供给存储器芯片,并且控制信号被提供给数据寄存器缓冲器。 根据本发明,由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短,可以实现相当高的数据传输速率。
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公开(公告)号:US20080164058A1
公开(公告)日:2008-07-10
申请号:US12004020
申请日:2007-12-20
申请人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
发明人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
IPC分类号: H05K1/11
CPC分类号: H05K1/112 , H05K1/0237 , H05K1/0298 , H05K2201/09227 , H05K2201/09236 , H05K2201/09518 , H05K2201/09627 , H05K2201/10159 , H05K2201/10734
摘要: A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring are arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.
摘要翻译: 一种用于安装存储器的多层印刷电路板,包括:布置布线的层叠布线层; 以及电连接至少两个所述布线层的多个层间连接部件。 多个层间连接部件中的至少一个是盲通孔。
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公开(公告)号:US09368185B2
公开(公告)日:2016-06-14
申请号:US14508744
申请日:2014-10-07
申请人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
发明人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
IPC分类号: G11C16/26 , G11C11/406
CPC分类号: G11C11/40615 , G11C11/40603 , G11C16/26
摘要: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.
摘要翻译: 半导体器件包括多个存储器单元,存取电路,被配置为对存储器单元执行数据读取操作,数据写入操作和数据刷新操作,所述存取电路以选择的第一模式操作 准备执行的第二模式和未准备好执行的第二模式;以及判断电路,被配置为响应于第一命令信息,以使得当访问电路处于第一模式时,访问电路执行数据刷新操作,以及 当访问电路处于第二模式时,访问电路从第二模式退出,然后执行刷新操作。
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公开(公告)号:US5494073A
公开(公告)日:1996-02-27
申请号:US267893
申请日:1994-07-06
申请人: Shunichi Saito
发明人: Shunichi Saito
CPC分类号: F16L37/35 , F16L37/34 , Y10T137/87949
摘要: A fluid connector is provided with a socket, a plug and a locking mechanism for locking the plug inserted in the socket. The socket has an axial passage and a first valve mechanism, for opening and closing the axial passage. The first valve mechanism includes a valve stem having one end fixed to the socket and the other end formed with a valve seat, a sleeve-like slide member movable in the axial passage with respect to the socket in a sealing state, a first packing provided on the slide member, for opening and closing the passage in cooperation with the valve seat, and urging means for urging the slide member toward the valve seat and causing it to abut against the first packing. The plug has an end portion capable of being inserted in the socket and a plug main body formed with an axial holes. A second valve mechanism for opening and closing the axial hole is provided in the plug main body. The second valve mechanism includes a valve member slidably provided in the plug main body and urged toward the end portion of the plug main body, and a second packing provided in the end portion of the plug main body, for retaining the valve member and closing the axial hole in cooperation with the valve member.
摘要翻译: 流体连接器设置有插座,插头和用于锁定插入插座中的插头的锁定机构。 插座具有轴向通道和用于打开和关闭轴向通道的第一阀机构。 第一阀机构包括阀杆,其一端固定到插座,另一端形成有阀座,套筒状滑动构件可在密封状态下相对于插座在轴向通道中移动,第一填料提供 在滑动构件上,用于与阀座协作地打开和关闭通道;以及推动装置,用于将滑动构件推向阀座并使其抵靠第一填料。 插头具有能够插入插座的端部和形成有轴向孔的插头主体。 用于打开和关闭轴向孔的第二阀机构设置在插头主体中。 第二阀机构包括可滑动地设置在插塞主体中并朝向插头主体的端部推压的阀构件,以及设置在插头主体的端部中的第二密封件,用于保持阀构件并且关闭 与阀构件协作的轴向孔。
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公开(公告)号:USD359797S
公开(公告)日:1995-06-27
申请号:US13184
申请日:1993-09-20
申请人: Shunichi Saito
设计人: Shunichi Saito
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公开(公告)号:US20150098289A1
公开(公告)日:2015-04-09
申请号:US14508744
申请日:2014-10-07
申请人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
发明人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi
IPC分类号: G11C11/406
CPC分类号: G11C11/40615 , G11C11/40603 , G11C16/26
摘要: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.
摘要翻译: 半导体器件包括多个存储器单元,存取电路,被配置为对存储器单元执行数据读取操作,数据写入操作和数据刷新操作,所述存取电路以选择的第一模式操作 准备执行的第二模式和未准备好执行的第二模式;以及判断电路,被配置为响应于第一命令信息,以使得当访问电路处于第一模式时,访问电路执行数据刷新操作,以及 当访问电路处于第二模式时,访问电路从第二模式退出,然后执行刷新操作。
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9.
公开(公告)号:US08422263B2
公开(公告)日:2013-04-16
申请号:US12801326
申请日:2010-06-03
申请人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号: G11C5/06
CPC分类号: G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要: A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译: 存储器模块包括多个存储器芯片,多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。 数据寄存器缓冲器与存储器芯片执行数据传输。 命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。 缓冲的命令/地址/控制信号被提供给存储器芯片,并且控制信号被提供给数据寄存器缓冲器。 根据本发明,由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短,可以实现相当高的数据传输速率。
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公开(公告)号:US20110205150A1
公开(公告)日:2011-08-25
申请号:US12861731
申请日:2010-08-23
申请人: Shunichi Saito , Shuji Miyamoto
发明人: Shunichi Saito , Shuji Miyamoto
CPC分类号: G11B19/042 , G11B21/12
摘要: According to one embodiment, an electronic device includes a main body unit, a hard disk drive housed inside the main body unit and including a head which performs reading and writing of data to a magnetic disk, a display unit pivotable between a first position where the display unit is laid parallel to the main body unit and a second position where the display unit is raised relative to the main body unit, a sensor which senses an angle at which the display unit is positioned, and a control unit. The control unit retracts the head to a retraction position when the sensor senses a change in the angle of the display unit.
摘要翻译: 根据一个实施例,电子设备包括主体单元,容纳在主体单元内的硬盘驱动器,并且包括执行数据到磁盘的读取和写入的头部,可在第一位置和第二位置之间转动的显示单元, 显示单元平行于主体单元放置,第二位置和显示单元相对于主体单元升高的第二位置,感测显示单元所在的角度的传感器和控制单元。 当传感器感测到显示单元的角度的变化时,控制单元将头部缩回到缩回位置。
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