公开(公告)号：US20170148754A1

公开(公告)日：2017-05-25

申请号：US15421737

申请日：2017-02-01

申请人： GlobalFoundries Inc.

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05113 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05613 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/014

摘要： Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

公开(公告)号：US11380615B2

公开(公告)日：2022-07-05

申请号：US17118876

申请日：2020-12-11

申请人： GLOBALFOUNDRIES INC.

发明人： Anthony K. Stamper ,  Daisy A. Vaughn ,  Stephen R. Bosley ,  Zhong-Xiang He

IPC分类号： H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01G4/33 ,  H01G4/08 ,  H01G4/232 ,  H01L23/528

摘要： The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

公开(公告)号：US11374111B2

公开(公告)日：2022-06-28

申请号：US16743293

申请日：2020-01-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

发明人： Xiuyu Cai ,  Chun-Chen Yeh ,  Qing Liu ,  Ruilong Xie

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L21/768 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165

摘要： A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

公开(公告)号：US20220200636A1

公开(公告)日：2022-06-23

申请号：US17556624

申请日：2021-12-20

申请人： GLOBALFOUNDRIES INC.

发明人： Abdellatif Bellaouar ,  Sher Jiun Fang ,  Frank Zhang

IPC分类号： H04B1/00 ,  H03F3/195 ,  H03G3/30 ,  H03L7/099 ,  H04B1/16

摘要： We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ⅔ the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ⅔ the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ⅓ the first frequency or about ⅓ the second frequency during the duty cycle.

公开(公告)号：US10998422B2

公开(公告)日：2021-05-04

申请号：US16730712

申请日：2019-12-30

申请人： GLOBALFOUNDRIES INC.

发明人： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC分类号： H01L21/70 ,  H01L29/66 ,  H01L27/02 ,  H01L21/8238

摘要： At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.

公开(公告)号：US20210111141A1

公开(公告)日：2021-04-15

申请号：US16599738

申请日：2019-10-11

申请人： GLOBALFOUNDRIES INC.

发明人： Wolfgang SAUTER ,  Mark W. KUEMERLE ,  Eric W. TREMBLE

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L25/065

摘要： The present disclosure relates to semiconductor structures and, more particularly, to partitioned substrates with interconnect bridge structures and methods of manufacture. The structure includes: a plurality of substrates; at least one chip bonded and electrically connected to each of the plurality of substrates; and an interconnect bridge that physically connects the plurality of substrates and electrically connects each of the plurality of chips bonded to each of the plurality of substrates.

公开(公告)号：US20210082532A1

公开(公告)日：2021-03-18

申请号：US16568394

申请日：2019-09-12

申请人： GLOBALFOUNDRIES INC.

发明人： Eric D. HUNT-SCHROEDER ,  Sebastian T. VENTRONE ,  James A. SVARCZKOPF ,  Igor ARSOVSKI

IPC分类号： G11C17/18

摘要： The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.

公开(公告)号：US20210074842A1

公开(公告)日：2021-03-11

申请号：US16568242

申请日：2019-09-11

申请人： GLOBALFOUNDRIES INC.

发明人： JIEHUI SHU

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234

摘要： A semiconductor device comprising a substrate with a first fin and a second fin disposed on the substrate. A gate electrode is over the first fin and the second fin. A gate-cut pedestal is positioned between the first fin and the second fin, the gate-cut pedestal having side surfaces and a top surface. A portion of the side surfaces of the gate-cut pedestal is covered by the gate electrode. The gate-cut pedestal has a height that is substantially similar to a height of the first fin or the second fin.

公开(公告)号：US20210066474A1

公开(公告)日：2021-03-04

申请号：US16551061

申请日：2019-08-26

申请人： GLOBALFOUNDRIES Inc.

发明人： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/737 ,  H01L21/02

摘要： Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

公开(公告)号：US20210066118A1

公开(公告)日：2021-03-04

申请号：US16553737

申请日：2019-08-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Michel J. Abou-Khalil ,  Aaron Vallett ,  Steven M. Shank ,  Bojidha Babu ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC分类号： H01L21/762 ,  H01L21/324 ,  H01L21/265 ,  H01L29/06

摘要： Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.