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    Inverse Phase Allotrope Rare Earth Magnets
    1.
    发明申请
    Inverse Phase Allotrope Rare Earth Magnets 审中-公开

    公开(公告)号：US20180277289A1

    公开(公告)日：2018-09-27

    申请号：US15782062

    申请日：2017-10-12

    申请人： Intermolecular, Inc.

    发明人： Abraham Anapolsky

    IPC分类号： H01F1/055 ,  H01F1/11 ,  H01F1/09 ,  H01F41/22 ,  H01F41/02

    CPC分类号： H01F1/0551 ,  H01F1/0556 ,  H01F1/09 ,  H01F1/11 ,  H01F41/0266 ,  H01F41/22

    摘要： Provided are inverse phase allotrope rare earth (IPARE) magnets, methods of forming thereof, and applications of IPARE magnets. Unlike conventional samarium-cobalt magnets, IPARE magnets maintain their hexagonal lattice structures over a range of equiatomic compositions, such as when concentrations of different elements are within 10 atomic % of each other. An IPARE magnet may comprise cobalt, iron, copper, nickel, and samarium and a concentration of cobalt may be between 17-27 atomic %. An IPARE magnet may be substantially free from zirconium and/or titanium. An IPARE magnet may be formed by quenching a molten mixture of its components. The quenching may be performed in a magnetic field. After quenching, the IPARE magnet may be machined. Furthermore, IPARE magnets may be used as a structural element, e.g. in an electric motor.

    Plasma cleaning of superconducting layers
    7.
    发明授权
    Plasma cleaning of superconducting layers 有权

    公开(公告)号：US09425376B2

    公开(公告)日：2016-08-23

    申请号：US14138672

    申请日：2013-12-23

    申请人： Intermolecular Inc.

    发明人： Frank Greer ,  Andy Steinbach

    IPC分类号： H01L39/24

    CPC分类号： H01L39/2493

    摘要： In a “window-junction” formation process for Josephson junction fabrication, a spacer dielectric is formed over the first superconducting electrode layer, then an opening (the “window” is formed to expose the part of the electrode layer to be used for the junction. In an atomic layer deposition (ALD) chamber (or multi-chamber sealed system) equipped with direct or remote plasma capability, the exposed part of the electrode is sputter-etched with Ar, H2, or a combination to remove native oxides, etch residues, and other contaminants. Optionally, an O2 or O3 pre-clean may precede the sputter etch. When the electrode is clean, the tunnel barrier layer is deposited by ALD in-situ without further oxidant exposure.

    Wet etching of silicon containing antireflective coatings
    8.
    发明授权
    Wet etching of silicon containing antireflective coatings 有权
    含硅抗反射涂层的湿蚀刻

    公开(公告)号：US09418865B2

    公开(公告)日：2016-08-16

    申请号：US14140737

    申请日：2013-12-26

    申请人： Intermolecular Inc. ,  International Business Machines Corporation

    发明人： Gregory Nowling ,  John Fitzsimmons

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31111 ,  H01L21/31133 ,  H01L21/67086

    摘要： Provided are methods for processing semiconductor substrates or, more specifically, etching silicon containing antireflective coatings (SiARCs) from the substrates while preserving silicon oxides layers disposed on the same substrates. An etching solution including sulfuric acid and hydrofluoric acid may be used for these purposes. In some embodiments, the weight ratio of sulfuric acid to hydrofluoric acid in the etching solution is between about 15:1 and 100:1 (e.g., about 60:1). The temperature of the etching solution may be between about 30° C. and 50° C. (e.g., about 40° C., during etching). It has been found that such processing conditions provide a SiARC etching rate of at least about 50 nanometers per minute and selectivity of SiARC over silicon oxide of greater than about 10:1 or even greater than about 50:1. The same etching solution may be also used to remove photoresist, organic dielectric, and titanium nitride.

    摘要翻译： 提供了用于处理半导体衬底的方法，或者更具体地，从衬底中蚀刻含硅抗反射涂层（SiARCs），同时保留设置在相同衬底上的氧化硅层。 包括硫酸和氢氟酸的蚀刻溶液可以用于这些目的。 在一些实施方案中，蚀刻溶液中硫酸与氢氟酸的重量比为约15:1至100:1（例如约60:1）。 蚀刻溶液的温度可以在约30℃至50℃之间（例如在蚀刻期间约为40℃）。 已经发现，这样的处理条件提供至少约50纳米每分钟的SiARC蚀刻速率，SiARC相对于氧化硅的选择性大于约10:1或甚至大于约50:1。 也可以使用相同的蚀刻溶液去除光致抗蚀剂，有机电介质和氮化钛。

    Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks
    10.
    发明授权
    Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks 有权
    基于缺陷和带工程金属 - 电介质金属叠层的交叉条阵列中的非易失性存储器的当前选择器

    公开(公告)号：US09397141B2

    公开(公告)日：2016-07-19

    申请号：US14294519

    申请日：2014-06-03

    申请人： Intermolecular, Inc.

    发明人： Imran Hashim ,  Venkat Ananthan ,  Tony P. Chiang ,  Prashant B. Phatak

    IPC分类号： H01L45/00 ,  H01L47/00 ,  H01L27/24 ,  H01L29/872

    CPC分类号： H01L27/2418 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/10

    摘要： Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

    摘要翻译： 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括夹在两个较低的漏电介质层之间的高泄漏电介质层。 低泄漏层可以起到限制低电压下选择器装置的电流的作用。 高泄漏电介质层可以用于在高电压下增强选择器装置上的电流。