公开(公告)号：US20090184760A1

公开(公告)日：2009-07-23

申请号：US12009721

申请日：2008-01-22

申请人： Henning M. Hauenstein

发明人： Henning M. Hauenstein

IPC分类号： H03L5/00

CPC分类号： B60W20/00 ,  B60K6/485 ,  B60L2240/425 ,  B60W10/08 ,  B60W10/30 ,  B60W2510/087 ,  H01L2224/4813 ,  H01Q1/2283 ,  H03K17/689 ,  Y02T10/6226 ,  Y02T10/642 ,  Y02T90/16

摘要： An automotive drive system for a high voltage electric motor comprises a microcontroller and ECU powered by a low voltage (12 volt) bus net which controls the drives of a high voltage inverter powered by a 100 volt or higher source, which, in turn, drives the motor. To provide good electrical insulation between the low voltage and high voltage systems, the low voltage control signals are produced by a low voltage signal transmitter chip which has a small integral antenna which wirelessly communicates with the antenna of a high voltage driver IC which drives the power devices of the high voltage inverter. The two IC chips are separated by a suitable isolation distance and may be bare chips, individually packaged chips or co-packed chips. Plural control IC chips and driver IC chips can communicate with one another for adverse control functions, including “smart” functions.

摘要翻译： 用于高压电动机的汽车驱动系统包括微控制器和由低压（12伏）总线网络供电的ECU，该总线控制由100伏特或更高电源供电的高压逆变器的驱动器，所述高压逆变器依次驱动 电机。 为了在低电压和高压系统之间提供良好的电绝缘，低压控制信号由低电压信号发射器芯片产生，该低电压信号发射器芯片具有小的整体天线，其与驱动电力的高电压驱动器IC的天线无线通信 高压变频器的设备。 这两个IC芯片被分隔开合适的隔离距离，并且可以是裸芯片，单独封装的芯片或共包芯片。 多个控制IC芯片和驱动器IC芯片可以彼此通信，用于不利的控制功能，包括“智能”功能。

公开(公告)号：US20070026577A1

公开(公告)日：2007-02-01

申请号：US11190602

申请日：2005-07-27

申请人： Richard Francis ,  Chiu Ng

发明人： Richard Francis ,  Chiu Ng

IPC分类号： H01L21/332

CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/41725 ,  H01L29/66333 ,  Y10S438/904

摘要： A process for forming an NPT IGBT in a thin N type silicon wafer in which the bottom surface of a thin silicon wafer (100 microns thick or less) has a shallow reduced lifetime region in its bottom formed by a light species atom implant to a depth of less than about 2.5 microns. A P+ transparent collector region about 0.5 microns deep is formed in the bottom of the damaged region by a boron implant. A collector contact of Al/Ti/NiV and Ag is sputtered onto the collector region and is annealed at 200° C. to 400° C. for 30 to 60 minutes. A pre-anneal step before applying the collector metal can be carried out in vacuum at 300° C. to 400° C. for 30 to 60 seconds.

摘要翻译： 一种用于在薄N型硅晶片中形成NPT IGBT的工艺，其中薄硅晶片（100微米厚或更小）的底表面在其底部具有浅的减少的寿命区域，其通过光物质原子注入形成深度 小于约2.5微米。 通过硼注入在损伤区域的底部形成约0.5微米深的P + 将Al / Ti / NiV和Ag的集电极触点溅射到集电极区域，并在200℃至400℃退火30至60分钟。 在施加集电体金属之前的预退火步骤可以在300℃至400℃的真空中进行30至60秒。

公开(公告)号：US20060208711A1

公开(公告)日：2006-09-21

申请号：US11301464

申请日：2005-12-13

申请人： Marco Soldano ,  Bing Lu

发明人： Marco Soldano ,  Bing Lu

IPC分类号： G05F1/613 ,  G05F3/16

CPC分类号： H02M1/4225 ,  H02M1/44 ,  H02M3/1584 ,  Y02B70/126

摘要： A circuit and method for improving EMI noise performance in a bridgeless PFC boost converter. Such a converter comprises a boost inductor having a first end connected to a first AC input terminal and a second end connected to a first junction defined between the anode of a first diode and a first terminal of a first switch; a second terminal of the first switch connected to a common line; a parallel circuit of a capacitance and a load connected between the cathode of the first diode and the common line; a series circuit of a second diode and a second switch connected between the cathode of the first diode and the common line; and a second AC input terminal connected to a second junction defined between the anode of the second diode and the second switch. High-frequency EMI noise is bypassed by placing a first filter capacitor between the first AC terminal and the common line. A second boost inductor may be connected between the second AC input terminal and the second junction, and a second filter capacitor may be connected between the second AC terminal and the common line. The first and/or second filter capacitor has a lower impedance in a high frequency range than the corresponding first or second boost inductor. Preferably the first and second capacitors have substantially the same capacitance.

摘要翻译： 一种用于提高无桥PFC升压转换器EMI噪声性能的电路和方法。 这种转换器包括升压电感器，其具有连接到第一AC输入端子的第一端和连接到第一二极管的阳极和第一开关的第一端子之间限定的第一结的第二端; 第一开关的第二端子连接到公共线; 连接在第一二极管的阴极和公共线之间的电容和负载的并联电路; 连接在第一二极管的阴极和公共线之间的第二二极管和第二开关的串联电路; 以及第二AC输入端子，其连接到限定在所述第二二极管的阳极和所述第二开关之间的第二连接点。 通过在第一AC端子和公共线路之间放置第一滤波电容器来绕过高频EMI噪声。 第二升压电感器可以连接在第二AC输入端子和第二连接点之间，并且第二滤波电容器可以连接在第二AC端子和公共线路之间。 第一和/或第二滤波电容器在高频范围内具有比相应的第一或第二升压电感器更低的阻抗。 优选地，第一和第二电容器具有基本相同的电容。

公开(公告)号：US20050280163A1

公开(公告)日：2005-12-22

申请号：US11144169

申请日：2005-06-03

申请人： Christopher Schaffer ,  Chuan Cheah ,  Kevin Hu

发明人： Christopher Schaffer ,  Chuan Cheah ,  Kevin Hu

IPC分类号： H01L23/34 ,  H01L23/48 ,  H01L23/538 ,  H01L25/16

CPC分类号： H01L25/162 ,  H01L23/5385 ,  H01L24/01 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： The semiconductor portion of a circuit includes a plurality of flip chip devices which are arranged in a planar fashion in a common housing. The plurality of flip chip devices are connected to each other without wire bonding. The common housing includes a packaging structure, the packaging structure including a connective portion and at least one web portion, which aids in the thermal management of the heat emitted by the plurality of flip chip devices and which connects the flip chip devices to each other. Passive devices in the circuit may also be arranged in a planar fashion in the common housing.

摘要翻译： 电路的半导体部分包括在共同的壳体中以平面方式布置的多个倒装芯片器件。 多个倒装芯片器件彼此连接而不引线接合。 公共壳体包括包装结构，该包装结构包括连接部分和至少一个卷筒纸部分，其有助于热管理由多个倒装芯片装置发出的热量，并将倒装芯片装置彼此​​连接。 电路中的无源器件也可以以平面方式布置在公共壳体中。

公开(公告)号：US20050269720A1

公开(公告)日：2005-12-08

申请号：US11141859

申请日：2005-06-01

申请人： Hugo Burke ,  Aram Arzumanian

发明人： Hugo Burke ,  Aram Arzumanian

IPC分类号： H01L21/301 ,  H01L21/44 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L23/544 ,  H01L23/58

CPC分类号： H01L23/585 ,  H01L21/78 ,  H01L23/296 ,  H01L23/544 ,  H01L23/562 ,  H01L24/11 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： A wafer containing a plurality of die separated by streets which are to be sawn has a nitride passivation layer which has openings over die contact locations and gaps leaving nitride strips along the streets. The gaps in the nitride along the streets expose an oxide, preferably TEOS. A nickel/gold plate contact material overlies the nitride layer and contacts the exposed die contact areas but does not adhere to either the nitride surface or the oxide surfaces. A saw blade can then cut along the streets without being gummed by the metalizing and without producing cracks which propagate into the die termination areas.

摘要翻译： 包含要被锯割的街道分开的多个模具的晶片具有氮化物钝化层，其在模具接触位置和开口处沿着街道留下氮化物带。 沿着街道的氮化物中的间隙暴露氧化物，优选TEOS。 镍/金板接触材料覆盖在氮化物层上并与暴露的裸片接触区域接触，但不粘附到氮化物表面或氧化物表面上。 然后，锯片可以沿着街道切割而不被金属化而胶合，并且不产生传播到模具终止区域中的裂纹。

公开(公告)号：US20050202637A1

公开(公告)日：2005-09-15

申请号：US11077929

申请日：2005-03-11

申请人： Davide Chiola

发明人： Davide Chiola

IPC分类号： H01L21/336

CPC分类号： H01L29/8725 ,  H01L29/0619 ,  H01L29/66143

摘要： A trench type Schottky device has a guard ring diffusion of constant depth between the outermost of an active trench and an outer surrounding termination trench. The junction curvature of the guard ring diffusion is suppressed or cut out by the trenches.

摘要翻译： 沟槽式肖特基器件具有在有源沟槽的最外部和外部周围终止沟槽之间的恒定深度的保护环扩散。 保护环扩散的接合曲率被沟槽抑制或切除。

公开(公告)号：US20050194636A1

公开(公告)日：2005-09-08

申请号：US11042993

申请日：2005-01-25

申请人： Daniel Kinzer

发明人： Daniel Kinzer

IPC分类号： H01L29/94

CPC分类号： H01L29/781 ,  H01L29/0653 ,  H01L29/423 ,  H01L29/4933

摘要： A power MOSFET is disclosed in which the source and drain regions are reversed from their usual positions and the drain is on the top of the chip (the surface containing the junction pattern diffusions) and the source is on the bottom of the chip. A plurality of spaced trenches are formed in the top surface. One group of trenches contain gate polysilicon and a gate oxide to control an invertible channel region along the trench. A second group of the trenches have a buried source contact at their bottoms which are connected between the N source material to the P channel region to short out a parasitic bipolar transistor.

摘要翻译： 公开了一种功率MOSFET，其中源极和漏极区域与其通常位置相反，并且漏极位于芯片的顶部（包含接合图案扩散的表面），并且源极在芯片的底部。 在顶表面中形成多个隔开的沟槽。 一组沟槽包含栅极多晶硅和栅极氧化物以控制沿着沟槽的可逆沟道区域。 第二组沟槽在其底部具有埋入的源极接触，其连接在N源材料到P沟道区域以短路寄生双极晶体管。

公开(公告)号：US20050173741A1

公开(公告)日：2005-08-11

申请号：US11052458

申请日：2005-02-07

申请人： Kyle Spring

发明人： Kyle Spring

IPC分类号： H01L29/76 ,  H01L29/78

CPC分类号： H01L29/781

摘要： A top drain MOSFET has active trenches with an enlarged width at the top of each trench which has a thicker oxide than the gate oxide adjacent the channel region. The thicker oxide at the top of the trench reduces Qgd. The thicker oxide at the top of the active trench also reduces the electronic field in the drain drift region.

摘要翻译： 顶漏MOSFET具有在每个沟槽的顶部具有扩大的宽度的有源沟槽，其具有比与沟道区相邻的栅极氧化物更厚的氧化物。 在沟槽顶部的较厚的氧化物减少了Qd。 有源沟槽顶部较厚的氧化物也减少漏极漂移区域中的电场。

公开(公告)号：US20050116217A1

公开(公告)日：2005-06-02

申请号：US10911170

申请日：2004-08-04

申请人： David Jones ,  Robert Haase

发明人： David Jones ,  Robert Haase

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L21/335 ,  H01L21/336 ,  H01L29/06 ,  H01L29/12 ,  H01L29/165 ,  H01L29/417 ,  H01L29/739 ,  H01L29/778

CPC分类号： H01L29/66431 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/7781 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7827

摘要： A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is converted to a gate oxide layer. The conduction channel formed by the SiGe layer is permanently strained to increase its mobility particularly hole mobility.

摘要翻译： MOS沟槽器件通过在沟槽的硅表面上形成小于约13nm厚的应变SiGe层，并且在SiGe层上形成薄（30nm或更小）的外延沉积硅的薄层，其外延 层被转换成栅极氧化物层。 由SiGe层形成的导电通道永久地应变以增加其迁移率，特别是空穴迁移率。

公开(公告)号：US20050009255A1

公开(公告)日：2005-01-13

申请号：US10885378

申请日：2004-07-06

申请人： Davide Chiola ,  Zhi He

发明人： Davide Chiola ,  Zhi He

IPC分类号： H01L21/283 ,  H01L21/04 ,  H01L21/316 ,  H01L21/321 ,  H01L21/329 ,  H01L21/338 ,  H01L29/47 ,  H01L29/872 ,  H01L31/0312

CPC分类号： H01L29/8725 ,  H01L21/32105 ,  H01L29/6606

摘要： The gate oxide in the trenches of a trench type Schottky device are formed by oxidizing a layer of polysilicon deposited in trenches of a silicon or silicon carbide substrate. A small amount of the substrate is also oxidized to create a good interface between the substrate and the oxide layer which is formed. The corners of the trench are rounded by the initial formation and removal of a sacrificial oxide layer.

摘要翻译： 通过氧化在硅或碳化硅衬底的沟槽中沉积的多晶硅层来形成沟槽型肖特基元件沟槽中的栅极氧化物。 少量的衬底也被氧化以在衬底和形成的氧化物层之间形成良好的界面。 通过初始形成和去除牺牲氧化物层，使沟槽的角部变圆。