公开(公告)号：US07821243B2

公开(公告)日：2010-10-26

申请号：US11624837

申请日：2007-01-19

Applicant: Masaki Shiraishi ,  Takayuki Hashimoto ,  Noboru Akiyama

Inventor： Masaki Shiraishi ,  Takayuki Hashimoto ,  Noboru Akiyama

IPC: G05F1/595

CPC classification number: H02M1/08 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H03K17/0822 ,  H03K17/165 ,  H03K17/166 ,  H03K17/6871 ,  H01L2924/00 ,  H01L2224/45099

Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.

Abstract translation: 在非隔离型DC / DC转换器中，从通过高侧MOSFET的主电路以外的部分施加驱动低侧MOSFET的栅极的低侧预驱动器的基准电位， 低侧MOSFET，使得低侧MOSFET的源极与预驱动器之间的寄生电感增加，而不增加主电路中的寄生电感的和，并且低侧MOSFET的栅极的负电位驱动 并且可以防止在不添加任何构件和改变驱动系统的情况下自启闭现象。

公开(公告)号：US07777346B2

公开(公告)日：2010-08-17

申请号：US12345917

申请日：2008-12-30

Applicant: Kensuke Ishikawa ,  Tatsuyuki Saito ,  Masanori Miyauchi ,  Toshio Saito ,  Hiroshi Ashihara

Inventor： Kensuke Ishikawa ,  Tatsuyuki Saito ,  Masanori Miyauchi ,  Toshio Saito ,  Hiroshi Ashihara

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/2855 ,  H01L21/76807 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.

Abstract translation: 在制造半导体集成电路器件时，在形成于半导体衬底上的第一级互连件上的层间绝缘膜中形成互连沟槽和接触孔，在沟槽和接触孔内部形成阻挡膜，使其膜 厚度从孔的底部的中心朝向接触孔底部的侧壁增加，在阻挡膜上形成铜膜，并且通过抛光形成第二级互连和连接器部分（插塞） 通过CMP。 以这种方式，通过连接器部分（插头）从第二级互连件流向第一级互连件的电流的几何最短路径与具有最低电阻的薄阻挡膜部分不一致，使得 电流路径可以分散，并且电子的浓度不容易发生。

公开(公告)号：US07834420B2

公开(公告)日：2010-11-16

申请号：US12335302

申请日：2008-12-15

Applicant: Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

Inventor： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

IPC: H01L29/00 ,  H01L21/8234

CPC classification number: H01L27/11 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/76895 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1104 ,  Y10S257/904

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract translation: 一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上 存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。 此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。 此外，通过使用诸如硅化的电阻降低装置来形成局部布线。 此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

公开(公告)号：US07833905B2

公开(公告)日：2010-11-16

申请号：US12435446

申请日：2009-05-05

Applicant: Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

Inventor： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC: H01L21/44

CPC classification number: H01L27/1104 ,  H01L27/11

Abstract: In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

Abstract translation: 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

公开(公告)号：USRE41869E1

公开(公告)日：2010-10-26

申请号：US12130782

申请日：2008-05-30

Applicant: Tetsuya Kawashima ,  Akira Mishima

Inventor： Tetsuya Kawashima ,  Akira Mishima

IPC: H01L23/02 ,  H01L23/12

CPC classification number: H01L24/40 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16245 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40249 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/49111 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.

Abstract translation: 在半导体装置中，控制功率MOSFET芯片2配置在输入侧板状引线5上，漏极端子DT1形成在芯片2的背面，源极端子ST1和栅极端子GT1为 形成在芯片2的主表面上，源极端子ST1连接到用于源极12的板状引线。此外，同步功率MOSFET芯片3设置在输出侧板状引线6上，并且 漏极端子DT2形成在芯片3的后表面上，并且输出侧板状引线6连接到漏极端子DT2。 此外，源极端子ST2和栅极端子GT2形成在同步功率MOSFET芯片3的主表面上，源极端子ST2连接到源极13的板状引线。源极12和13的板状引线 被曝光，因此可以提高MCM 1的散热能力。

公开(公告)号：US07745903B2

公开(公告)日：2010-06-29

申请号：US12503674

申请日：2009-07-15

Applicant: Tetsuo Adachi ,  Akihiko Sato

Inventor： Tetsuo Adachi ,  Akihiko Sato

IPC: H01L21/76

CPC classification number: H01L27/112 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11253 ,  H01L27/11293 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

Abstract: A technique is provided which permits formation within a single chip both a field effect transistor of high reliability capable of suppressing the occurrence of a crystal defect and a field effect transistor of a high integration degree. In a mask ROM section having an element isolation region with an isolation width of smaller than 0.3 μm, a planar shape of each active region ACT is made polygonal by cutting off the corners of a quadrangle, thereby suppressing the occurrence of a crystal defect in the active region ACT and diminishing a leakage current flowing between the source and drain of a field effect transistor. In a sense amplifier data latch section which is required to have a layout of a small margin in the alignment between a gate G of a field effect transistor and the active region ACT, the field effect transistor is disposed at a narrow pitch by making the active region ACT quadrangular.

Abstract translation: 提供了允许在单个芯片内形成能够抑制晶体缺陷的发生的高可靠性的场效应晶体管和高集成度的场效应晶体管的技术。 在具有隔离宽度小于0.3μm的元件隔离区域的掩模ROM区域中，通过切断四边形的角部，使各有源区域ACT的平面形状为多边形，从而抑制了在 有源区ACT并且减小在场效应晶体管的源极和漏极之间流动的漏电流。 在场效应晶体管的栅极G与有源区域ACT之间的对准中需要具有较小余量的布局的读出放大器数据锁存部分中，通过使该场效应晶体管处于活动状态 区域ACT四边形。

公开(公告)号：US20110281541A1

公开(公告)日：2011-11-17

申请号：US13105633

申请日：2011-05-11

Applicant: Jonathan Borremans

Inventor： Jonathan Borremans

IPC: H04B1/10

CPC classification number: H04B1/18

Abstract: An adaptive front-end architecture for a receiver is disclosed. In one embodiment, the adaptive front-end architecture includes an input configured to receive an input signal and a linear low-noise amplifier connected to the input and configured to amplify the input signal to produce an amplified input signal. The adaptive front-end architecture further includes a first passive mixer arrangement configured to generate first a local oscillator signal and mix the first local oscillator signal with the amplified input signal to produce a first baseband output signal. The adaptive front-end architecture further includes a second passive mixer arrangement configured to generate a second local oscillator signal and mix the second local oscillator signal with the input signal to produce a second baseband output signal. The adaptive front-end architecture further includes a baseband impedance component configured to filter the first baseband signal and/or the second baseband signal using impedance translation.

Abstract translation: 公开了一种用于接收机的自适应前端架构。 在一个实施例中，自适应前端架构包括被配置为接收输入信号的输入端和连接到输入端并被配置为放大输入信号以产生放大输入信号的线性低噪声放大器。 自适应前端架构还包括被配置为首先生成本地振荡器信号并将第一本地振荡器信号与放大的输入信号混合以产生第一基带输出信号的第一无源混频器装置。 自适应前端架构还包括被配置为产生第二本地振荡器信号并将第二本地振荡器信号与输入信号混合以产生第二基带输出信号的第二无源混频器装置。 自适应前端架构还包括基带阻抗分量​​，其被配置为使用阻抗平移来对第一基带信号和/或第二基带信号进行滤波。

公开(公告)号：US20110255694A1

公开(公告)日：2011-10-20

申请号：US13172217

申请日：2011-06-29

Applicant: Shigenori Miyauchi ,  Atsuo Yamaguchi

Inventor： Shigenori Miyauchi ,  Atsuo Yamaguchi

IPC: H04L9/00

CPC classification number: H04L9/0894 ,  H04L2209/12 ,  H04L2209/16 ,  H04L2209/34

Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

Abstract translation: 编码/解码操作部分包括编码/解码操作电路和用于迂回编码解码操作电路的避免路径，并且可以在编码/解码操作电路中的编码或解码输入数据之间进行选择，并且迂回编码/解码操作电路以输出 输入数据无变化。 必须从选择器向键存储部分和初始化矢量存储部分提供一条线。 利用这种结构，可以实现一种编码/解码电路，其可以抑制用于将密钥数据的内容发送到密钥存储部分和初始化向量存储部分的电线数量的增加，并且不会引起并发症 电路布局。

公开(公告)号：US08022542B2

公开(公告)日：2011-09-20

申请号：US11543794

申请日：2006-10-06

Applicant: Kazumi Saitou

Inventor： Kazumi Saitou

IPC: H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76849 ,  H01L23/53266 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate, an interlayer insulating film, a tungsten film, a first barrier metal film, a second barrier metal film and a metal wiring film. The interlayer insulating film is formed on the semiconductor substrate, and has an opening. The tungsten film is embedded in the opening. The first barrier metal film is formed on the tungsten film and excludes a Ti film. The second barrier metal film is formed on the first barrier metal film and is a Ti-containing film. The metal wiring film is formed on the second barrier metal film.

Abstract translation: 半导体器件包括半导体衬底，层间绝缘膜，钨膜，第一阻挡金属膜，第二阻挡金属膜和金属布线膜。 层间绝缘膜形成在半导体基板上，并具有开口。 钨膜嵌入开口。 第一阻挡金属膜形成在钨膜上，不包括Ti膜。 第二阻挡金属膜形成在第一阻挡金属膜上，并且是含Ti膜。 金属布线膜形成在第二阻挡金属膜上。

公开(公告)号：US07972920B2

公开(公告)日：2011-07-05

申请号：US12700344

申请日：2010-02-04

Applicant: Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

Inventor： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC: H01L21/8244 ,  G11C11/40

CPC classification number: H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract translation: 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。