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公开(公告)号：US20220108975A1
公开(公告)日：2022-04-07
申请号：US17492356
申请日：2021-10-01
发明人： Cristina MANOLA , Rosa Lucia TORRISI , Simone RASCUNÀ , Gabriele BELLOCCHI , Annalinda CONTINO , Giuseppe MACCARRONE
IPC分类号： H01L23/00 , H01L23/495 , B22F9/24 , B22F1/00
摘要： The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200° C. and in some embodiments at about 150° C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.
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公开(公告)号：US12130360B2
公开(公告)日：2024-10-29
申请号：US18178110
申请日：2023-03-03
CPC分类号： G01S15/931 , G01S7/521 , G01S7/524 , G01S2007/52007 , G01S2015/937 , H04R17/00
摘要： In accordance with an embodiment, an ultrasound transmitter device includes a transformer comprising a secondary winding configured to be coupled to a piezoelectric transducer; a plurality of transistors coupled to the primary winding of the transformer and to a ground terminal via a sense resistor; an amplifier having an output coupled to control nodes of the plurality of transistors, a first input coupled to the sense resistor, and second input coupled to a reference resistor; a switching circuit configured to alternately couple control nodes of the plurality of transistors to an output of amplifier and to a reference node via complementary pulse signals, wherein the switching circuit is configured to turn on and turn off the plurality of transistors and operate the plurality of transistors in a push-pull manner; and a digital-to-analog converter having an output coupled to the reference resistor.
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3.发明授权公开(公告)号：US12125803B2
公开(公告)日：2024-10-22
申请号：US18121145
申请日：2023-03-14
发明人： Paolo Crema
IPC分类号： H01L23/495 , B23K26/0622 , B23K26/354 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , B23K103/08
CPC分类号： H01L23/562 , B23K26/0622 , B23K26/354 , H01L21/4825 , H01L21/565 , H01L23/3114 , H01L23/49503 , H01L23/49513 , H01L23/49582 , B23K2103/08
摘要： A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.
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公开(公告)号：US12124713B2
公开(公告)日：2024-10-22
申请号：US18057390
申请日：2022-11-21
发明人： Francesco Bombaci , Andrea Tosoni
IPC分类号： G06F3/06
CPC分类号： G06F3/0629 , G06F3/0622 , G06F3/0665 , G06F3/0679
摘要： A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.
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公开(公告)号：US12119746B2
公开(公告)日：2024-10-15
申请号：US17807466
申请日：2022-06-17
发明人： Marco Borghese , Mattia Carrera
CPC分类号： H02M3/158 , H02M1/0016 , H02M1/0022 , H02M1/0025
摘要： In an embodiment a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, which is a comparison signal, indicative of a variation of a regulated output voltage of an electronic voltage regulator with respect to the reference voltage and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, and a pulse-width modulated (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal proportional to an input voltage signal at an input node of the electronic voltage regulator and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal.
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公开(公告)号：US12117942B2
公开(公告)日：2024-10-15
申请号：US18109675
申请日：2023-02-14
IPC分类号： G06F12/14
CPC分类号： G06F12/1441 , G06F12/1458
摘要： A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.
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7.发明授权公开(公告)号：US12113103B2
公开(公告)日：2024-10-08
申请号：US18062524
申请日：2022-12-06
IPC分类号： H01L29/06 , H01L21/265 , H01L21/266 , H01L29/10 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L29/1095 , H01L29/66734 , H01L29/7813
摘要： A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal.
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公开(公告)号：US12106201B2
公开(公告)日：2024-10-01
申请号：US17039653
申请日：2020-09-30
发明人： Carmine Cappetta , Thomas Boesch , Giuseppe Desoli
CPC分类号： G06N3/04 , G06F9/3806 , G06F13/1657 , G06F13/1673 , G06F13/4022 , G06N3/063 , G06T7/11 , G06T2207/20084
摘要： A convolutional accelerator framework (CAF) has a plurality of processing circuits including one or more convolution accelerators, a reconfigurable hardware buffer configurable to store data of a variable number of input data channels, and a stream switch coupled to the plurality of processing circuits. The reconfigurable hardware buffer has a memory and control circuitry. A number of the variable number of input data channels is associated with an execution epoch. The stream switch streams data of the variable number of input data channels between processing circuits of the plurality of processing circuits and the reconfigurable hardware buffer during processing of the execution epoch. The control circuitry of the reconfigurable hardware buffer configures the memory to store data of the variable number of input data channels, the configuring including allocating a portion of the memory to each of the variable number of input data channels.
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公开(公告)号：US12101104B2
公开(公告)日：2024-09-24
申请号：US17721110
申请日：2022-04-14
发明人： Roberto Modaffari , Paolo Pesenti
IPC分类号： H03M3/00
摘要： A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.
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公开(公告)号：US12085393B2
公开(公告)日：2024-09-10
申请号：US17198160
申请日：2021-03-10
CPC分类号： G01C21/206 , A61B5/1118 , A61B5/681 , G01C5/06 , A61B2560/0209 , A61B2560/0257 , A61B2562/0219
摘要： A user context and/or activity detection device envisages a pressure sensor, configured to provide a pressure signal; an electrostatic-charge-variation sensor, configured to provide a charge-variation signal indicative of a variation of electrostatic charge associated with the user; and a processing unit, which is coupled to the pressure sensor and to the electrostatic-charge-variation sensor so as to receive the pressure signal and the charge-variation signal and is configured to jointly process the pressure signal and charge-variation signal for detecting changes in level or altitude.
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