公开(公告)号：US20240363156A1

公开(公告)日：2024-10-31

申请号：US18770651

申请日：2024-07-12

申请人： Etron Technology, Inc. ,  Invention And Collaboration Laboratory Pte. Ltd.

发明人： Chao-Chun Lu ,  Chun Shiah ,  Bor-Doou Rong

IPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

摘要： The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

公开(公告)号：US20240347100A1

公开(公告)日：2024-10-17

申请号：US18629445

申请日：2024-04-08

申请人： Micron Technology, Inc.

发明人： Yuan He ,  Yang Lu ,  Dong Pan ,  Kang-Yong Kim

IPC分类号： G11C11/4076 ,  G11C11/406 ,  G11C11/408

CPC分类号： G11C11/4076 ,  G11C11/40622 ,  G11C11/4085

摘要： A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.

公开(公告)号：US12119046B2

公开(公告)日：2024-10-15

申请号：US18045541

申请日：2022-10-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaeduk Yu ,  Yohan Lee ,  Yonghyuk Choi ,  Jiho Cho

IPC分类号： G11C16/34 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096

CPC分类号： G11C11/4085 ,  G11C11/4074 ,  G11C11/4096

摘要： A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.

公开(公告)号：US12119037B2

公开(公告)日：2024-10-15

申请号：US17937120

申请日：2022-09-30

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Jixing Chen

IPC分类号： G11C11/406 ,  G11C11/408 ,  H03K19/20

CPC分类号： G11C11/406 ,  G11C11/4087 ,  H03K19/20

摘要： A refresh circuit includes a refresh counter configured to output address signals through a plurality of address pins; an address mixer configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal; and an address pre-decoding circuit configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.

公开(公告)号：US20240331758A1

公开(公告)日：2024-10-03

申请号：US18451112

申请日：2023-08-17

申请人： SK hynix Inc.

发明人： Young Ook SONG ,  Jae Geun YUN

IPC分类号： G11C11/408 ,  G06F7/501 ,  G11C11/406

CPC分类号： G11C11/408 ,  G06F7/501 ,  G11C11/406

摘要： A memory module includes a plurality of memory devices each including a plurality of rows; and a plurality of row counters each configured to count a number of accesses to a corresponding row among the plurality of rows, and each configured to be distributed and disposed in the plurality of memory devices.

公开(公告)号：US12106797B2

公开(公告)日：2024-10-01

申请号：US17859153

申请日：2022-07-07

申请人： INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY

发明人： Seong Ook Jung ,  In Jun Jung ,  Tae Hyun Kim

IPC分类号： G11C11/34 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4094 ,  H03K19/017

CPC分类号： G11C11/4093 ,  G11C11/4085 ,  G11C11/4094 ,  H03K19/01742

摘要： A bit line sense amplifier includes: a first inverter having an input terminal connected to a first sensing node and an output terminal connected to a second inner bit line; a second inverter having an input terminal connected to a second sensing node and an output terminal connected to a first inner bit line; a first capacitor connected between the first sensing node and the first inner bit line; a second capacitor connected between the second sensing node and the second inner bit line; an isolation unit configured to cut off a connection between the first inner bit line and a second bit line; and an offset cancellation unit configured to connect the first sensing node to the second inner bit line, the first inner bit line to the first bit line, the second sensing node to the first inner bit line, and the second inner bit line to the second bit line.

公开(公告)号：US12101945B2

公开(公告)日：2024-09-24

申请号：US18225186

申请日：2023-07-24

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC分类号： H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/408 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70

CPC分类号： H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L29/24 ,  H01L29/7869 ,  H10B41/20 ,  H10B41/70

摘要： [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US12094514B2

公开(公告)日：2024-09-17

申请号：US17884053

申请日：2022-08-09

申请人： Winbond Electronics Corp.

发明人： Chih-Chiang Lai

IPC分类号： G11C11/406 ,  G11C11/408

CPC分类号： G11C11/40615 ,  G11C11/40611 ,  G11C11/4085 ,  G11C11/4087 ,  G11C2211/4067

摘要： A memory device coupled to a memory controller and including a memory array and an access circuit is provided. The memory array includes a plurality of cells. Each of the cells is coupled to a word-line. The access circuit is coupled between the memory controller and the memory array. In a normal mode, the access circuit executes a refresh action for the cells which are coupled to at least one word-line in response to the memory controller outputting an auto-refresh command. In a standby mode, the access circuit selects one of the word-lines and determines whether to execute the refresh action for the cells coupled to the selected word-line according to the retention capability of the selected word-line at regular time intervals.

公开(公告)号：US12087353B2

公开(公告)日：2024-09-10

申请号：US17885709

申请日：2022-08-11

申请人： Arm Limited

发明人： Edward Martin McCombs, Jr. ,  Andrew David Tune ,  Sean James Salisbury ,  Rahul Mathur ,  Hsin-Yu Chen ,  Phani Raja Bhushan Chalasani

IPC分类号： G11C11/00 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

摘要： A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

公开(公告)号：US12087350B2

公开(公告)日：2024-09-10

申请号：US17032191

申请日：2020-09-25

申请人： Intel Corporation

发明人： William Waller ,  Cheng-Yi Huang

IPC分类号： G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4094

CPC分类号： G11C11/4087 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4085 ,  G11C11/4094

摘要： Systems, apparatuses and methods may provide for a multi-deck non-volatile memory architecture with an improved wordline bus and bitline bus configuration. For example, wordline busses and bitline busses may be positioned so as to be located over the junctions between two tiles, e.g., between a memory tile and a termination tile and between two memory tiles. Additionally, multi-deck non-volatile memory architectures may utilize data shifting to select which one of a plurality of wordline drivers and a plurality of bitline drivers are in communication with a data circuit of each memory tile. In a configuration where wordline busses and bitline busses have been positioned so as to be located over the junctions between two tiles, such data shifting directions may be able to be implemented with a limited number of shifting direction.