公开(公告)号：WO2006005062A2

公开(公告)日：2006-01-12

申请号：PCT/US2005/023755

申请日：2005-06-30

Applicant: CREE, INC. ,  IBBETSON, James ,  KELLER, Bernd ,  PARIKH, Primit

Inventor： IBBETSON, James ,  KELLER, Bernd ,  PARIKH, Primit

IPC: H01L33/00

CPC classification number: H01L33/486 ,  H01L23/481 ,  H01L24/48 ,  H01L33/62 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12035 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A packaged light emitting device includes a carrier substrate having a top surface and a bottom surface, first and second conductive vias extending from the top surface of the substrate to the bottom surface of the substrate, and a bond pad on the top surface of the substrate in electrical contact with the first conductive via. A diode having first and second electrodes is mounted on the bond pad with the first electrode is in electrical contact with the bond pad. A passivation layer is formed on the diode, exposing the second electrode of the diode. A conductive trace is formed on the top surface of the carrier substrate in electrical contact with the second conductive via and the second electrode. The conductive trace is on and extends across the passivation layer to contact the second electrode. Methods of packaging light emitting devices include providing an epiwafer including a growth substrate and an epitaxial structure on the growth substrate, bonding a carrier substrate to the epitaxial structure of the epiwafer, forming a plurality of conductive vias through the carrier substrate, defining a plurality of isolated diodes in the epitaxial structure, and electrically connecting at least one conductive via to respective ones of the plurality of isolated diodes.

Abstract translation: 封装的发光器件包括具有顶表面和底表面的载体衬底，从衬底的顶表面延伸到衬底的底表面的第一和第二导电通孔以及衬底的顶表面上的接合焊盘 与第一导电通孔电接触。 具有第一和第二电极的二极管安装在接合焊盘上，第一电极与接合焊盘电接触。 在二极管上形成钝化层，使二极管的第二电极露出。 导电迹线形成在载体基板的顶表面上，与第二导电通孔和第二电极电接触。 导电迹线在钝化层上并且延伸穿过第二电极。 封装发光器件的方法包括在生长衬底上提供包括生长衬底和外延结构的外延膜，将载体衬底结合到外延膜的外延结构，形成通过载体衬底的多个导电通孔，限定多个 隔离二极管，并且将至少一个导电通孔电连接到多个隔离二极管中的相应二极管。

公开(公告)号：WO2004019412A1

公开(公告)日：2004-03-04

申请号：PCT/US2003/026866

申请日：2003-08-26

Applicant: CALIFORNIA MICRO DEVICES CORPORATION

Inventor： WHITWORTH, Adam, John ,  SHERRIMA, Faraj, A. ,  CHALAKA, Ashok, Kumar

IPC: H01L29/22

CPC classification number: H01L23/60 ,  H01L24/48 ,  H01L25/167 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12035 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: An apparatus consisting of a single wire bond silicon sub-mount used to make an LED device which also has built-in ESD protection in the sub-mount. The single wire bond silicon sub-mount uses a pass-through interconnection between the topside of the sub-mount and the underside so that the LED chip mounted thereon is electrically coupled through the sub-mount to the anode.

Abstract translation: 一种由单引线接合硅子座组成的装置，用于制造在子座中也具有内置ESD保护的LED器件。 单线接合硅子座安装在子座的顶侧和下侧之间使用通过互连，使得其上安装的LED芯片通过子座电连接到阳极。

公开(公告)号：WO0042659A9

公开(公告)日：2001-06-21

申请号：PCT/US0000999

申请日：2000-01-15

Applicant: BROADCOM CORP ,  WOO AGNES N ,  KINDSFATER KENNETH R ,  LU FANG ,  VORENKAMP PIETER

Inventor： WOO AGNES N ,  KINDSFATER KENNETH R ,  LU FANG ,  VORENKAMP PIETER

IPC: H01F17/00 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08 ,  H03B5/12 ,  H03B5/36 ,  H03D7/16 ,  H03D7/18 ,  H03G1/00 ,  H03H11/12 ,  H03J3/08 ,  H03J3/18 ,  H03L7/10 ,  H03L7/23

CPC classification number: H03L7/23 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L24/06 ,  H01L27/0248 ,  H01L2224/05554 ,  H01L2924/12034 ,  H01L2924/12035 ,  H01L2924/14 ,  H01L2924/3011 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H01L2924/00

Abstract: An integrated circuit ESD protection system comprises: a local power supply bus, a local ground bus, a first local ESD clamp, and ESD ground bus disposed between local power supply and ground busses and coupled to the local power supply bus through the first local ESD clamp, and coupled to the local ground bus through the second ESD clamp. The local power supply bus, the local ground bus, the first ESD clamp, the second ESD clamp and the ESD ground bus are disposed on a substrate. A reduced capacitance bonding pad is disposed on the substrate. A shunting ggNMOS ESD structure triggered by a divider circuit comprises a gate boosting structure disposed in an n-well that is coupled to the bonding pad.

Abstract translation: 集成电路ESD保护系统包括：本地电源总线，本地接地总线，第一本地ESD钳位电路和设置在本地电源和接地总线之间的ESD接地总线，并通过第一本地ESD耦合到本地电源总线 并通过第二个ESD钳位耦合到本地接地总线。 本地电源总线，本地接地总线，第一ESD钳位，第二ESD钳位和ESD接地总线设置在基板上。 在该基板上设置有降低电容的焊盘。 由分压器电路触发的分流ggNMOS ESD结构包括设置在耦合到接合焊盘的n阱中的栅极升压结构。

公开(公告)号：WO01024253A1

公开(公告)日：2001-04-05

申请号：PCT/EP2000/009110

申请日：2000-09-15

IPC: H01L21/66 ,  H01L21/60 ,  H01L21/822 ,  H01L23/58 ,  H01L27/02 ,  H01L27/04 ,  H01L29/78

CPC classification number: H01L24/49 ,  H01L22/32 ,  H01L24/06 ,  H01L24/48 ,  H01L27/0255 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12035 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device, e.g. power transistor (1, Fig. 1), has a gate or other electrode (4) connected via a test pad (15B) to a set of parallel fingers (21A-21F) in a first portion of a bond pad (12). An ESD protection device (13) is connected via a test pad (15C) to a set of parallel fingers (22A-22C) in a second portion of the bond pad (12). A voltage clamping protection device (14) is connected via a test pad (15A) to a set of parallel fingers (23A-23C) in a third portion of the bond pad (12). The three sets of fingers overlap in an interdigitated pattern defining a bond pad area (24). The transistor (1) and the protection devices (13, 14) may be independently tested and then connected to a same terminal (7C) by a wire (16) bonded over a rectangular bonded region (25) extending across the bond pad area (24). This arrangement allows for a large misalignment in the bond process while still achieving connection of the three bond pad portions.

Abstract translation: 半导体器件，例如 功率晶体管（1，图1）具有通过测试焊盘（15B）连接到接合焊盘（12）的第一部分中的一组平行指（21A-21F）的栅极或其他电极（4）。 ESD保护装置（13）经由测试焊盘（15C）连接到接合焊盘（12）的第二部分中的一组平行指状物（22A-22C）。 电压钳位保护装置（14）经由测试焊盘（15A）连接到接合焊盘（12）的第三部分中的一组平行指状物（23A-23C）。 三组手指以限定接合焊盘区域（24）的交错图案重叠。 晶体管（1）和保护器件（13,14）可以独立测试，然后通过接合在延伸穿过接合焊盘区域的矩形接合区域（25）上的导线（16）连接到相同的端子（7C） 24）。 这种布置允许粘合过程中的大的未对准，同时仍然实现三个焊盘部分的连接。

公开(公告)号：WO1997024762A1

公开(公告)日：1997-07-10

申请号：PCT/DE1996002139

申请日：1996-11-09

Applicant: ROBERT BOSCH GMBH ,  SPITZ, Richard ,  SCHULER, Siegfried

Inventor： ROBERT BOSCH GMBH

IPC: H01L23/049

CPC classification number: H01L23/049 ,  H01L23/24 ,  H01L24/00 ,  H01L2924/12035 ,  H01L2924/351 ,  H01L2924/00

Abstract: The invention relates to a rectifier diode which has a base (2) and which can be pressed into a provided opening of a rectifier arrangement. A platform (3) forming one part with the base is arranged on the base, and a semiconductor chip (4) is secured to said platform and is connected to a head wire (8). According to the invention, a wall (9) surrounding the platform is provided which ensures a low, homogenous level of bending strain on the supporting surface of the chip, and in comparison with a wall-free structure, said wall leads to uncritical centring of the chip during production. Moreover, semiconductor chips which are not that well centred no longer alter the reliability of the rectifier diode.

Abstract translation: 本发明涉及一种具有基座（2），其被压入提供了一种用于整流器布置的开口的整流二极管，与（3）在基片与设置在插座，被安装在它的一部分，在半导体芯片上的平台（4） 又与一个头布线（8）连接。 在本发明的设计，围绕所述壁（9）的平台提供，相比于无墙Chipzentrierung使得在制造非关键的结构这确保了低和加压和均匀的弯曲应力施加到管芯支撑表面中。 不如为中心的半导体芯片不再用于整流器二极管的可靠性的障碍。