公开(公告)号：WO2005053373A2

公开(公告)日：2005-06-16

申请号：PCT/IB2004/004394

申请日：2004-12-02

Applicant: UNITED TEST AND ASSEMBLY CENTER ,  TAN, Hien Boon ,  WANG, Chuen Khiang ,  BIDIN, Rahamat ,  SUN, Anthony Yi Sheng ,  CHONG, Desmond Yok Rue ,  KOLAN, Ravi Kanth

Inventor： TAN, Hien Boon ,  WANG, Chuen Khiang ,  BIDIN, Rahamat ,  SUN, Anthony Yi Sheng ,  CHONG, Desmond Yok Rue ,  KOLAN, Ravi Kanth

CPC classification number: H01L23/3114 ,  H01L21/76897 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/8191 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.

Abstract translation: 公开了一种制造芯片级封装的方法。 该方法包括将晶片切割成多个芯片阵列，每个阵列包括两个或多个集成电路芯片。 该方法还包括将每个阵列安装在基板上并将附接到基板的每个阵列切割成单独的芯片级封装，每个单独的芯片级封装仅包括一个集成电路芯片。

公开(公告)号：WO2006035321A3

公开(公告)日：2006-07-20

申请号：PCT/IB2005003992

申请日：2005-05-05

Applicant: UNITED TEST & ASSEMBLY CT LTD ,  KOLAN RAVI KANTH ,  TAN HIEN BOON ,  SUN YI-SHENG ANTHONY ,  KUAN LIM BENG ,  SHIVALINGAM KRISHNAMURTHY

Inventor： KOLAN RAVI KANTH ,  TAN HIEN BOON ,  SUN YI-SHENG ANTHONY ,  KUAN LIM BENG ,  SHIVALINGAM KRISHNAMURTHY

IPC: H01L23/31

CPC classification number: H01L21/566 ,  H01L23/3114 ,  H01L23/4334 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/013

Abstract: A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free form encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.

Abstract translation: 芯片级集成电​​路封装包括具有第一面和第二面的集成电路芯片。 在集成电路芯片的第一面上形成多个柱状凸块。 封装材料封装集成电路芯片的侧面和第一面以及柱状凸块。 柱状凸块的上端保持游离形式的密封剂材料，并且由密封剂材料的上表面和柱状凸块的上端形成基本平坦的表面。 多个焊球安装在与柱状凸块的上端对应的位置上的基本平坦的表面上。

公开(公告)号：WO2010080068A1

公开(公告)日：2010-07-15

申请号：PCT/SG2009/000021

申请日：2009-01-12

Applicant: KOLAN, Ravi, Kanth

Inventor： KOLAN, Ravi, Kanth

IPC: H01L23/31 ,  H01L23/522 ,  H01L25/04

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/051 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A Wafer level stacked package (200), comprising a main silicon chip (101 ) having first face and second face and having plurality of dielectric and metal trace patterns on first (122) and second faces (126). The silicon chip having plurality of through silicon metal filled vias linking (130), the metal trace patterns of first and second faces of the main silicon chip. The silicon chip having plurality of bumps (140) at the first face. The silicon chip having a bottom encapsulant member (150) covering the first face and the bumps, with bump connections extended outside the encapsulant surface and with bottom encapsulant extending sideways and exactly equal to the size of the main silicon chip.

Abstract translation: 一种晶片级堆叠封装（200），包括具有第一面和第二面的主硅芯片（101），并且在第一（122）和第二面（126）上具有多个电介质和金属迹线图案。 所述硅芯片具有连接（130）多个通过硅金属的通孔，所述主硅芯片的第一和第二面的金属迹线图案。 所述硅芯片在所述第一面处具有多个凸起（140）。 所述硅芯片具有覆盖所述第一面和所述凸起的底部密封剂构件（150），所述凸起连接在所述密封剂表面外延伸，并且底部密封剂侧向延伸并且正好等于所述主硅芯片的尺寸。

公开(公告)号：WO2005053373A3

公开(公告)日：2007-12-21

申请号：PCT/IB2004004394

申请日：2004-12-02

Applicant: UNITED TEST AND ASSEMBLY CT ,  TAN HIEN BOON ,  WANG CHUEN KHIANG ,  BIDIN RAHAMAT ,  SUN ANTHONY YI SHENG ,  CHONG DESMOND YOK RUE ,  KOLAN RAVI KANTH

Inventor： TAN HIEN BOON ,  WANG CHUEN KHIANG ,  BIDIN RAHAMAT ,  SUN ANTHONY YI SHENG ,  CHONG DESMOND YOK RUE ,  KOLAN RAVI KANTH

IPC: H01L21/00 ,  H01L29/34 ,  H01L29/40

CPC classification number: H01L23/3114 ,  H01L21/76897 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/8191 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.

Abstract translation: 公开了一种制造芯片级封装的方法。 该方法包括将晶片切割成多个芯片阵列，每个阵列包括两个或多个集成电路芯片。 该方法还包括将每个阵列安装在基板上并将附接到基板的每个阵列切割成单独的芯片级封装，每个单独的芯片级封装仅包括一个集成电路芯片。

公开(公告)号：WO2006035321A2

公开(公告)日：2006-04-06

申请号：PCT/IB2005/003992

申请日：2005-05-05

Applicant: UNITED TEST AND ASSEMBLY CENTER, LTD. ,  KOLAN, Ravi, Kanth ,  TAN, Hien, Boon ,  SUN, Yi-sheng, Anthony ,  KUAN, Lim, Beng ,  SHIVALINGAM, Krishnamurthy

Inventor： KOLAN, Ravi, Kanth ,  TAN, Hien, Boon ,  SUN, Yi-sheng, Anthony ,  KUAN, Lim, Beng ,  SHIVALINGAM, Krishnamurthy

CPC classification number: H01L21/566 ,  H01L23/3114 ,  H01L23/4334 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2224/13099 ,  H01L2924/013 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free form encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.

Abstract translation: 芯片级集成电​​路封装包括具有第一面和第二面的集成电路芯片。 在集成电路芯片的第一面上形成多个柱状凸块。 封装材料封装集成电路芯片的侧面和第一面以及柱状凸块。 柱状凸块的上端保持自由形式的密封剂材料，并且通过密封剂材料的上表面和柱状凸块的上端形成大致平坦的表面。 多个焊球安装在基本平坦的表面上对应于柱形凸块上端的位置上。