公开(公告)号：WO2013078750A1

公开(公告)日：2013-06-06

申请号：PCT/CN2012/000019

申请日：2012-01-06

Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO. LTD ,  WANG, Xinchao ,  LIANG, Zhizhong

Inventor： WANG, Xinchao ,  LIANG, Zhizhong

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/50 ,  H01L21/56

CPC classification number: H01L23/49541 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/0781 ,  H01L2224/85 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method is disclosed for manufacturing a first-plating-then-etching quad flat no-lead (QFN) packaging structure. The method includes providing a metal substrate, forming a first photoresist film on a top surface of the metal substrate, and forming a plating pattern in the first photoresist film using photolithography. The method also includes forming a first metal layer containing a plurality of inner leads by a first multi-layer electrical plating process using the plating pattern in the first photoresist film as a mask such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the method includes attaching at least one die in a predetermined region on the top surface of the metal substrate, connecting the die and the plurality of inner leads using metal wires by a wire bonding process, and sealing the die, the plurality of inner leads, and metal wires with a molding compound. The method also includes forming a second metal layer on a back surface of the metal substrate by a second multi-layer electrical plating process and, after forming the second metal layer, etching the metal substrate from the back surface of the metal substrate to form a plurality of I/O pads with pre-formed second metal layer corresponding to the plurality of inner leads. Further, the method includes filling sealant in etched areas at the back surface of the metal substrate.

Abstract translation: 公开了一种用于制造第一镀层 - 然后蚀刻四方扁平无铅（QFN）封装结构的方法。 该方法包括提供金属基板，在金属基板的顶表面上形成第一光致抗蚀剂膜，以及使用光刻法在第一光致抗蚀剂膜中形成电镀图案。 该方法还包括通过使用第一光致抗蚀剂膜中的电镀图案作为掩模的第一多层电镀工艺形成包含多个内部引线的第一金属层，使得多个内部引线的引线间距显着减小 。 此外，该方法包括在金属基板的上表面上的规定区域内附加至少一个管芯，通过引线接合工艺使用金属线连接管芯和多个内部引线，并且密封管芯， 引线和带有模塑料的金属线。 该方法还包括通过第二多层电镀工艺在金属基板的背面上形成第二金属层，在形成第二金属层之后，从金属基板的背面蚀刻金属基板，形成 多个具有对应于多个内引线的预先形成的第二金属层的I / O焊盘。 此外，该方法包括在金属基板的背面的蚀刻区域中填充密封剂。

公开(公告)号：WO2013078752A1

公开(公告)日：2013-06-06

申请号：PCT/CN2012/000021

申请日：2012-01-06

Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO. LTD ,  WANG, Xinchao ,  LIANG, ZHIZHONG

Inventor： WANG, Xinchao ,  LIANG, ZHIZHONG

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/4952 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48163 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/0781 ,  H01L2224/45101 ,  H01L2224/85 ,  H01L2924/00012

Abstract: A no-exposed-pad quad flat no-lead (QFN) packaging structure is disclosed. The no- exposed-pad QFN packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of I/O pads formed based on the metal substrate and extends to proximity of the die. The no-exposed-pad QFN packaging structure also includes a first metal layer, which contains a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the no-exposed-pad QFN packaging structure includes metal wires connecting the die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads. The die, the plurality of inner leads, and metal wires are sealed with a molding compound.

Abstract translation: 公开了一种无曝光焊盘四边形无引线（QFN）封装结构。 无曝光焊盘QFN封装结构包括金属基板，耦合到金属基板的顶表面的第一裸片以及基于金属基板形成并延伸到模具附近的多个I / O焊盘。 无暴露焊盘的QFN封装结构还包括第一金属层，其包含对应于多个I / O焊盘并且延伸到裸片附近的多个内引线，并且通过多金属层形成在金属基板上， 使得多个内引线的引线间距显着减小。 此外，无裸露焊盘QFN封装结构包括连接管芯和多个内部引线的金属线，以及形成在多个I / O焊盘的背面上的第二金属层。 模具，多根内部引线和金属线用模塑料密封。

公开(公告)号：WO2013037187A1

公开(公告)日：2013-03-21

申请号：PCT/CN2012/001161

申请日：2012-08-28

Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO. LTD ,  WANG, Xinchao ,  LIANG, Zhizhong

Inventor： WANG, Xinchao ,  LIANG, Zhizhong

IPC: H01L21/60 ,  H01L23/495

CPC classification number: H01L24/97 ,  H01L21/4828 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method is provided for manufacturing a lead frame structure (100) in a semiconductor packaging process. The method includes providing a metal substrate having a top surface and a back surface, forming a top surface etching pattern and a back surface etching pattern. The method also includes performing an etching process to form an island (1) and a plurality of leads (2). Outer leads of the plurality of leads (2) on the back surface extend to the proximity of the island (1) such that a length of the outer leads is greater than a length of inner leads of the plurality of leads (2) on the top surface by a predetermined amount. Further, the method includes encapsulating the etched metal substrate using a molding compound exposing top surfaces and back surfaces of the island (1) and the plurality of leads (2).

Abstract translation: 提供了一种用于在半导体封装工艺中制造引线框架结构（100）的方法。 该方法包括提供具有顶表面和后表面的金属基底，形成顶表面蚀刻图案和背面蚀刻图案。 该方法还包括执行蚀刻工艺以形成岛（1）和多个引线（2）。 后表面上的多个引线（2）的外引线延伸到岛（1）的附近，使得外引线的长度大于多个引线（2）的内引线的长度， 上表面预定量。 此外，该方法包括使用暴露岛（1）和多个引线（2）的顶表面和后表面的模制化合物来封装蚀刻的金属基底。

公开(公告)号：WO2013037183A1

公开(公告)日：2013-03-21

申请号：PCT/CN2012/001157

申请日：2012-08-28

Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO. LTD ,  WANG, Xinchao ,  LIANG, Zhizhong

Inventor： WANG, Xinchao ,  LIANG, Zhizhong

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/49558 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/49861 ,  H01L24/03 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for manufacturing a lead frame structure(lOO) for semiconductor packaging includes providing a metal substrate and performing an etching process on the top surface and the back surface of the metal substrate simultaneously using a top surface etching pattern and a back surface etching pattern as the respective masks to form etched regions in the metal substrate, an island(l), and a plurality of leads(2). Further, the method includes placing the etched metal substrate in a mold, and encapsulating the etched metal substrate using the mold such that a molding compound(4) is filled in the etched regions, areas between the island and the plurality of leads, and areas between the plurality of leads, while exposing the top surfaces and the back surfaces of the island and the plurality of leads. The method also includes performing a plating process on the encapsulated metal substrate to form a first metal layer(5) on the exposed top surfaces of the island and the plurality of leads, and a second metal layer(6) on the exposed back surfaces of the island and the plurality of leads.

Abstract translation: 制造用于半导体封装的引线框架结构（100）的方法包括：使用顶表面刻蚀图案和背面蚀刻图案同时使用金属基板并在金属基板的顶表面和背面上进行蚀刻处理 各个掩模在金属基板，岛（1）和多个引线（2）中形成蚀刻区域。 此外，该方法包括将蚀刻的金属基板放置在模具中，并且使用模具封装蚀刻的金属基板，使得模制化合物（4）填充在蚀刻区域中，岛和多个引线之间的区域以及区域 在多个引线之间，同时暴露岛和多个引线的顶表面和后表面。 该方法还包括对封装的金属基板执行电镀处理以在岛和多个引线的暴露的顶表面上形成第一金属层（5），以及在暴露的背面上的第二金属层（6） 岛和多个线索。

公开(公告)号：WO2013078753A1

公开(公告)日：2013-06-06

申请号：PCT/CN2012/000022

申请日：2012-01-06

Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO.LTD ,  WANG, Xinchao ,  LIANG, Zhizhong

Inventor： WANG, Xinchao ,  LIANG, Zhizhong

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L23/49575 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/82 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49589 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00012

Abstract: A barrel-plating quad flat no-lead(QFN) package structure and a method for manufacturing the same are provided. The method includes: providing a metal substrate for a plurality of QFN components; forming a first photoresist film on a top surface of the substrate; forming a plating pattern in the first photoresist film; forming a first metal layer containing a plurality of inner leads(4); etching the substrate from the back surface of the substrate to form a plurality of I/O pads(2); filling sealant(lO) in etched areas; attaching at least one die(5) in a predetermined region on the top surface of the substrate; connecting the die and the inner leads using metal wires(6); sealing the die, the inner leads, and the metal wires with molding compound; separating the QFN components into individual QFN components; and forming a second metal layer(9) on the back surface of the I/O pads.

Abstract translation: 提供了滚镀四面扁平无引线（QFN）封装结构及其制造方法。 该方法包括：提供用于多个QFN分量的金属基板; 在所述基板的顶表面上形成第一光致抗蚀剂膜; 在所述第一光致抗蚀剂膜中形成电镀图案; 形成包含多个内引线（4）的第一金属层; 从衬底的背面蚀刻衬底以形成多个I / O焊盘（2）; 在蚀刻区域填充密封剂（10）; 将至少一个模具（5）附接在所述基板的顶表面上的预定区域中; 使用金属丝（6）连接管芯和内部引线; 用模塑料密封模具，内引线和金属线; 将QFN组件分离成单独的QFN组件; 以及在所述I / O焊盘的背面上形成第二金属层（9）。

公开(公告)号：WO2013075383A1

公开(公告)日：2013-05-30

申请号：PCT/CN2012/000018

申请日：2012-01-06

Applicant: JIANGSU CHANGJIANG ELELCTRONICS TECHNOLOGY CO. LTD ,  WANG, Xinchao ,  LIANG, Zhizhong

Inventor： WANG, Xinchao ,  LIANG, Zhizhong

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49513 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/60 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A quad flat no-lead (QFN) packaging structure and a method for manufacturing the same are provided. The QFN packaging structure includes a metal substrate, a first outer die pad (1) formed based on the metal substrate, and a first die (5) coupled to a top surface of the first outer die pad (1). The QFN packaging structure also includes a plurality of input/output (I/O) pads (2) formed based on the metal substrate, and a first metal layer containing a plurality of inner leads (4) corresponding to the plurality of I/O pads (2) and extending to proximity of the first die (5). The first metal layer is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads (4) is significantly reduced. Further, the QFN packaging structure includes metal wires (6) connecting the first die (5) and the plurality of inner leads (4), and a second metal layer (9) formed on a back surface of the plurality of I/O pads (2) and the first die pad (1). The first die (5), the plurality of inner leads (4), and metal wires (6) are sealed with a molding compound (7).

Abstract translation: 提供四边形无引线（QFN）封装结构及其制造方法。 所述QFN封装结构包括金属基板，基于所述金属基板形成的第一外部管芯焊盘（1）和与所述第一外部管芯焊盘（1）的顶面相连接的第一管芯（5）。 QFN封装结构还包括基于金属基板形成的多个输入/输出（I / O）焊盘（2）和包含多个对应于多个I / O的多个内部引线（4）的第一金属层 垫（2）并延伸到第一模（5）的附近。 通过多层电镀工艺在金属基板上形成第一金属层，使得多个内引线（4）的引线间距显着减小。 此外，QFN封装结构包括连接第一管芯（5）和多个内部引线（4）的金属线（6）和形成在多个I / O焊盘的背面上的第二金属层（9） （2）和第一管芯焊盘（1）。 第一模具（5），多个内部引线（4）和金属丝（6）用模制化合物（7）密封。

公开(公告)号：WO2013037186A1

公开(公告)日：2013-03-21

申请号：PCT/CN2012/001160

申请日：2012-08-28

Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO. LTD ,  WANG, Xinchao ,  LIANG, Zhizhong

Inventor： WANG, Xinchao ,  LIANG, Zhizhong

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L24/97 ,  H01L21/4828 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for manufacturing an islandless lead frame structure (100) for semiconductor packaging includes providing a metal substrate, forming a first photoresist film on the top surface of the metal substrate, and forming a top surface plating pattern in the first photoresist film using photolithography. The metal also includes performing a plating process on the top surface and the back surface of the metal substrate to form a first metal layer (5) on the top surface and a second metal layer (6) on the back surface. Further, the method includes performing an etching process on the top surface and the back surface of the metal substrate simultaneously using a top surface etching pattern and a back surface etching pattern as the respective masks to form etched regions in the metal substrate and a plurality of leads (2), without forming any island. Further, the method includes removing the third photoresist film and the fourth photoresist film, and pre-encapsulating the etched metal substrate using a molding compound (4) to form the pre-encapsulated lead frame structure.

Abstract translation: 一种用于半导体封装的无岛引线框架结构（100）的制造方法包括提供金属基板，在金属基板的顶表面上形成第一光致抗蚀剂膜，以及使用光刻法在第一光致抗蚀剂膜中形成顶表面电镀图案。 金属还包括在金属基板的顶表面和背表面上进行电镀处理，以在顶表面上形成第一金属层（5），并在后表面上形成第二金属层（6）。 此外，该方法包括使用顶表面刻蚀图案和背面蚀刻图案同时对金属基板的顶表面和背表面进行蚀刻处理，以在金属基板中形成蚀刻区域，并且多个 引线（2），不形成岛。 此外，该方法包括去除第三光致抗蚀剂膜和第四光致抗蚀剂膜，并使用模塑料（4）预先封装蚀刻的金属基板以形成预封装引线框架结构。

公开(公告)号：WO2013037185A1

公开(公告)日：2013-03-21

申请号：PCT/CN2012/001159

申请日：2012-08-28

Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO. LTD ,  WANG, Xinchao ,  LIANG, Zhizhong

Inventor： WANG, Xinchao ,  LIANG, Zhizhong

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L24/97 ,  H01L21/4828 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/01047 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A method for manufacturing a lead frame structure for semiconductor packaging includes providing a metal substrate, and performing a plating process on the top surface and the back surface of the metal substrate to form a first metal layer on the top surface and a second metal layer on the back surface. Further, the method includes performing an etching process on the top surface and the back surface of the metal substrate simultaneously using a top surface etching pattern and a back surface etching pattern as the respective masks to form etched regions in the metal substrate, an island, and a plurality of leads. Further, the method includes removing the third photoresist film and the fourth photoresist film, and pre-encapsulating the etched metal substrate using a molding compound to form the pre-encapsulated lead frame structure.

Abstract translation: 一种半导体封装用引线框架结构体的制造方法，其特征在于，在金属基板的顶面和背面设置金属基板，对其进行电镀处理，在顶面形成第一金属层，在第二金属层上形成第二金属层 背面。 此外，该方法包括使用顶表面蚀刻图案和背面蚀刻图案同时对金属基板的顶表面和背表面进行蚀刻处理作为各个掩模，以在金属基板，岛中形成蚀刻区域， 和多个引线。 此外，该方法包括去除第三光致抗蚀剂膜和第四光致抗蚀剂膜，并且使用模塑料预封装蚀刻的金属基板以形成预封装引线框架结构。

公开(公告)号：WO2013037184A1

公开(公告)日：2013-03-21

申请号：PCT/CN2012/001158

申请日：2012-08-28

Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO. LTD ,  WANG, Xinchao ,  LIANG, Zhizhong

Inventor： WANG, Xinchao ,  LIANG, Zhizhong

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L21/4828 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract:  A method for manufacturing an islandless lead frame structure (100) for semiconductor packaging includes providing a metal substrate, and performing an etching process on the top surface and the back surface of the metal substrate simultaneously using a top surface etching pattern and a back surface etching pattern as the respective masks to form etched regions in the metal substrate and a plurality of leads (2), without forming an island. Further, the method includes placing the etched metal substrate in a mold, and encapsulating the etched metal substrate using the mold such that a molding compound (4) is filled in the etched regions and areas between the plurality of leads (2), while exposing top surfaces and back surfaces of the plurality of leads (2). The method also includes performing a plating process on the encapsulated metal substrate to form a first metal layer (5) on the exposed top surfaces of the plurality of leads (2), and a second metal layer (6) on the exposed back surfaces of the plurality of leads (2).

Abstract translation: 制造用于半导体封装的无孤岛引线框架结构（100）的方法包括提供金属基板，并且使用顶表面蚀刻图案和背面蚀刻同时对金属基板的顶表面和背表面进行蚀刻处理 图案作为各个掩模，以在金属基板中形成蚀刻区域和多个引线（2），而不形成岛。 此外，该方法包括将蚀刻的金属基板放置在模具中，并且使用模具封装蚀刻的金属基板，使得模制化合物（4）填充在多个引线（2）之间的蚀刻区域和区域中，同时曝光 多个引线（2）的顶表面和后表面。 该方法还包括对封装的金属基板执行电镀处理以在多个引线（2）的暴露的顶表面上形成第一金属层（5），并且在暴露的背面上的第二金属层（6） 多个引线（2）。

公开(公告)号：WO2013078751A1

公开(公告)日：2013-06-06

申请号：PCT/CN2012/000020

申请日：2012-01-06

Applicant: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO.LTD ,  WANG, Xinchao ,  LIANG, Zhizhong

Inventor： WANG, Xinchao ,  LIANG, Zhizhong

IPC: H01L23/495

CPC classification number: H01L24/17 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49589 ,  H01L24/11 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/0781 ,  H01L2224/85 ,  H01L2924/00012

Abstract: A no-exposed-pad ball grid array (BGA) packaging structure is disclosed. The no-exposed- pad BGA packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of outer leads formed based on the metal substrate and extends to proximity of the die. The no-exposed-pad BGA packaging structure also includes a metal layer, which contains a plurality of inner leads corresponding to the plurality of outer leads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the no-exposed-pad BGA packaging structure includes metal wires connecting the die and the plurality of inner leads, and a plurality of solder balls attached to a back surface of the plurality of outer leads and the die pad. The die, the plurality of inner leads, and metal wires are sealed with a molding compound.

Abstract translation: 公开了一种无曝光焊盘球栅阵列（BGA）封装结构。 无曝光焊盘BGA封装结构包括金属基板，耦合到金属基板的顶表面的第一裸片以及基于金属基片形成并延伸到模具附近的多个外引线。 无曝光焊盘BGA封装结构还包括金属层，该金属层包含对应于多个外引线的多个内引线并延伸到模具附近，并通过多层电镀形成在金属基板上 处理使得多个内引线的引线间距显着减小。 此外，无曝光焊盘BGA封装结构包括连接管芯和多个内部引线的金属线，以及附接到多个外部引线和管芯焊盘的背面的多个焊球。 模具，多根内部引线和金属线用模塑料密封。