BUMP BONDS FORMED AS METAL LINE INTERCONNECTS IN A SEMICONDUCTOR DEVICE
    3.
    发明申请
    BUMP BONDS FORMED AS METAL LINE INTERCONNECTS IN A SEMICONDUCTOR DEVICE 审中-公开
    作为半导体器件中的金属线互连形成的BUMP

    公开(公告)号:WO2015179294A3

    公开(公告)日:2016-01-14

    申请号:PCT/US2015031377

    申请日:2015-05-18

    摘要: A semiconductor power chip has a semiconductor power device (210, 530, 720, 730, 830, 840) (e.g., a power-FET device) formed on a semiconductor die (10); wherein the semiconductor power device (210, 530, 720, 730, 830, 840) comprises an array of conductive contact elements (230A, 230B, 230C); a passivation layer (250) formed over the plurality of conductive contact elements (230A, 230B, 230C), the passivation layer (250) comprising passivation openings (12, 252) over a plurality of the conductive contact elements (230A, 230B, 230C); and an array of conductive bumps (200, 200a', 200c', 200e', 200A, 200B', 200C) including one or more interconnection bumps (200a', 200c', 200e', 200A, 200B', 200C), wherein each interconnection bump (200a', 200c', 200e', 200A, 200B', 200C) is formed over the passivation layer (250) and extends into at least two of the passivation openings (12, 252) and into contact with at least two underlying conductive contact elements (230A, 230B, 230C) to thereby provide a conductive coupling between the at least two underlying conductive contact elements (230A, 230B, 230C). The array of conductive contact elements (230A, 230B, 230C) may comprise at least one gate contact element (230A), at least one drain contact element (230B) and at least one source contact element (230C). The semiconductor power chip may further comprise a lead- frame (104, 510, 610, 710, 810) coupled to the array of conductive bumps (200, 200a', 200c', 200e', 200A, 200B', 200C) such that the one or more interconnection bumps (200a', 200c', 200e', 200A, 200B', 200C) provide a conductive coupling between at least a portion of the array of conductive contact elements (230A, 230B, 230C) and the lead-frame (104, 510, 610, 710, 810).

    摘要翻译: 半导体功率芯片具有形成在半导体管芯(10)上的半导体功率器件(210,530,720,730,830,840)(例如功率FET器件)。 其中所述半导体功率器件(210,530,720,730,830,840)包括导电接触元件阵列(230A,230B,230C); 形成在所述多个导电接触元件(230A,230B,230C)上方的钝化层(250),所述钝化层(250)包括多个导电接触元件(230A,230B,230C)上的钝化开口(12,252) ); 以及包括一个或多个互连凸块(200a',200c',200e',200A,200B',200C)的导电凸块(200,200a',200c',200e',200A,200B',200C) 每个互连突起(200a',200c',200e',200A,200B',200C)形成在钝化层(250)上并且延伸到至少两个钝化开口(12,252)中并且至少与 两个底层导电接触元件(230A,230B,230C),从而在所述至少两个下面的导电接触元件(230A,230B,230C)之间提供导电耦合。 导电接触元件阵列(230A,230B,230C)可以包括至少一个栅极接触元件(230A),至少一个漏极接触元件(230B)和至少一个源极接触元件(230C)。 半导体功率芯片还可以包括耦合到导电凸块阵列(200,200a',200c',200e',200A,200B',200C)的引线框架(104,510,610,710,810),使得 所述一个或多个互连凸块(200a',200c',200e',200A,200B',200C)提供导电接触元件阵列的至少一部分(230A,230B,230C) 框架(104,510,610,710,810)。