公开(公告)号：WO2010068699A3

公开(公告)日：2010-08-26

申请号：PCT/US2009067386

申请日：2009-12-09

Applicant: VERTICAL CIRCUITS INC ,  LEAL JEFFREY S ,  MCGRATH SCOTT ,  PANGRLE SUZETTE

Inventor： LEAL JEFFREY S ,  MCGRATH SCOTT ,  PANGRLE SUZETTE

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L24/76 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/76155 ,  H01L2224/82007 ,  H01L2224/82102 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by applying an electrically conductive material in an aerosol form, in contact with pads on the die or on the die and the substrate, and passing between the respective pads. In some embodiments a fillet is formed at the inside corner formed by an interconnect sidewall of the die and a surface inboard from pads on an underlying feature (underlying die or support); and the electrically conductive material passes over a surface of the fillet.

Abstract translation: 通过以气溶胶形式施加导电材料，例如通过气溶胶喷射印刷，在半导体管芯上形成互连端子。 而且，通过施加与气泡形式的导电材料，与模具上的焊盘或模具上的焊盘接触，形成堆叠裸片之间或芯片之间的电互连，以及下层支撑件（例如封装衬底）中的电路之间的电互连 基板，并在相应的焊盘之间通过。 在一些实施例中，在由模具的互连侧壁形成的内角处形成圆角，并且在底层特征（下面的模具或支撑件）上的垫的表面内侧形成圆角; 并且导电材料经过圆角的表面。

公开(公告)号：WO2009035849A2

公开(公告)日：2009-03-19

申请号：PCT/US2008/074450

申请日：2008-08-27

Applicant: VERTICAL CIRCUITS, INC. ,  CRANE, Scott, Jay ,  MCELREA, Simon, J., S. ,  MCGRATH, Scott ,  PAN, Weiping ,  MELCHER, De Ann, Eileen ,  ROBINSON, Marc, E.

Inventor： CRANE, Scott, Jay ,  MCELREA, Simon, J., S. ,  MCGRATH, Scott ,  PAN, Weiping ,  MELCHER, De Ann, Eileen ,  ROBINSON, Marc, E.

IPC: H01L23/12

CPC classification number: H01L24/83 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/27452 ,  H01L2224/29005 ,  H01L2224/29006 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A conformal coating on a semiconductor die provides adhesion between the die and a support. No additional adhesive is necessary to affix the die on the support. The conformal coating protects the die during assembly, and serves to electrically insulate the die from electrically conductive parts that the die may contact. The conformal coating may be an organic polymer, such as a parylene, for example. Also, a method for adhering a die onto a support, which may optionally be another die, includes providing a coating of a conformal between the die and the support, and heating the coating between the die and the support. The conformal coating may be provided on a die attach area of a surface of the die, or on a die mount region of a surface of the support, or on both a die attach area of a surface of the die and on a die mount region of a surface of the support; and the conformal coating may be provided following placement of the die on the support.

Abstract translation: 半导体管芯上的保形涂层提供了管芯和支撑件之间的粘附。 不需要额外的粘合剂将模具固定在支撑件上。 共形涂层在组装期间保护模具，并且用于使模具与模具可接触的导电部件电绝缘。 保形涂层可以是有机聚合物，例如聚对二甲苯。 此外，将模具粘附到可任选地是另一个模具的支撑件上的方法包括在模具和支撑件之间提供共形的涂层，以及加热模具和支撑件之间的涂层。 保形涂层可以设置在模具的表面的芯片附着区域上，或者设置在支撑体的表面的模具安装区域上，或者在模具的表面的芯片附着区域上以及模具安装区域 的支撑体的表面; 并且可以在将模具放置在支撑件上之后提供保形涂层。

公开(公告)号：WO2011146579A3

公开(公告)日：2012-02-23

申请号：PCT/US2011036941

申请日：2011-05-18

Applicant: VERTICAL CIRCUITS INC ,  CO REYNALDO ,  LEAL JEFFREY S ,  PANGRLE SUZETTE K ,  MCGRATH SCOTT ,  MELCHER DEANN EILEEN ,  BARRIE KEITH L ,  VILLLAVICENCIO GRANT ,  DEL ROSARIO ELMER M ,  BRAY JOHN R

Inventor： CO REYNALDO ,  LEAL JEFFREY S ,  PANGRLE SUZETTE K ,  MCGRATH SCOTT ,  MELCHER DEANN EILEEN ,  BARRIE KEITH L ,  VILLLAVICENCIO GRANT ,  DEL ROSARIO ELMER M ,  BRAY JOHN R

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Abstract translation: 在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。 而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。 而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

公开(公告)号：WO2009026171A3

公开(公告)日：2009-02-26

申请号：PCT/US2008/073365

申请日：2008-08-15

Applicant: VERTICAL CIRCUITS, INC. ,  CASKEY, Terrence ,  ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.s. ,  MCGRATH, Scott ,  ROBINSON, Marc ,  SCOTT, Mark ,  DU, Yong ,  JONES, Roydn ,  TRAN, Thanh, Van

Inventor： CASKEY, Terrence ,  ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.s. ,  MCGRATH, Scott ,  ROBINSON, Marc ,  SCOTT, Mark ,  DU, Yong ,  JONES, Roydn ,  TRAN, Thanh, Van

IPC: H01L23/12

Abstract: Apparatus for making electrical interconnection of semiconductor die includes a transfer carrier having an electrically conductive material arranged in a pattern on a transfer surface. A transfer process for electrical interconnect includes steps of aligning the transfer apparatus with an edge of a die to be interconnected; and moving the transfer apparatus toward the die edge (or moving the die edge toward the transfer apparatus, or moving both the transfer carrier and the die edge in relation to one another) to bring the patterned conductive material on the transfer surface and interconnect terminals on the die into contact. In some embodiments the carrier is left in place in a functioning interconnected device; in other embodiments the transfer carrier and the die edge are separated to leave at least a portion of the conductive material in contact with the interconnect terminals.

公开(公告)号：WO2008157779A2

公开(公告)日：2008-12-24

申请号：PCT/US2008/067722

申请日：2008-06-20

Applicant: VERTICAL CIRCUITS, INC. ,  ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.S. ,  CASKEY, Terrence ,  MCGRATH, Scott ,  DU, Yong

Inventor： ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.S. ,  CASKEY, Terrence ,  MCGRATH, Scott ,  DU, Yong

IPC: H01L27/00 ,  H01L27/10

CPC classification number: G01R1/0483 ,  H01L24/02 ,  H01L24/16 ,  H01L24/31 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2224/03

Abstract: Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g., die-to-substrate); and assemblies including a stack of at least two such devices interconnected die-to-die, or such a stack of devices electrically interconnected to underlying circuitry. Also, apparatus and methods for testing such a die.

Abstract translation: 可堆叠集成电路器件包括具有在有源（正面）侧上的互连焊盘的集成电路管芯，该管芯具有在管芯的前侧和管芯侧壁的连接处的前侧边缘， 模具的背面与侧壁的结合; 芯片还包括电连接到互连焊盘并且在模具的前侧边缘上延伸的导电迹线。 在一些实施例中，导电迹线还在侧壁上延伸，并且在一些这样的实施例中，导电迹线还在模具的背侧边缘上延伸，并且在一些这样的实施例中，导电迹线还在模具的背面延伸。 一个或两个模边可被倒角。 另外，制造这种装置的方法。 而且，包括这样的器件的组件电连接到底层电路（例如，裸片到衬底）; 以及包括至少两个这样的设备的堆叠的组件，这些设备互相连接到芯片上，或者这样一组电器件互连到下面的电路。 另外，用于测试这种模具的装置和方法。

公开(公告)号：WO2011146579A2

公开(公告)日：2011-11-24

申请号：PCT/US2011/036941

申请日：2011-05-18

Applicant: VERTICAL CIRCUITS, INC. ,  CO, Reynaldo ,  LEAL, Jeffrey, S. ,  PANGRLE, Suzette, K. ,  MCGRATH, Scott ,  MELCHER, DeAnn, Eileen ,  BARRIE, Keith, L. ,  VILLLAVICENCIO, Grant ,  DEL ROSARIO, Elmer, M. ,  BRAY, John, R.

Inventor： CO, Reynaldo ,  LEAL, Jeffrey, S. ,  PANGRLE, Suzette, K. ,  MCGRATH, Scott ,  MELCHER, DeAnn, Eileen ,  BARRIE, Keith, L. ,  VILLLAVICENCIO, Grant ,  DEL ROSARIO, Elmer, M. ,  BRAY, John, R.

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Abstract translation: 在晶片级处理中在芯片焊盘上形成连接器的方法包括在芯片焊盘上形成可固化的导电材料的点并且延伸到互连芯片边缘上或之上; 固化导电材料; 并且在切割步骤之后切断斑点。 而且，通过这些方法形成的管芯焊盘到z-互连连接器，并相应地成形和尺寸。 而且，堆叠的模具组件和包含根据方法制备的模具的堆叠模具组件，并且具有通过所述方法形成并且形状和尺寸的模具垫到z互连连接器。

公开(公告)号：WO2010068699A2

公开(公告)日：2010-06-17

申请号：PCT/US2009/067386

申请日：2009-12-09

Applicant: VERTICAL CIRCUITS, INC. ,  LEAL, Jeffrey, S. ,  MCGRATH, Scott ,  PANGRLE, Suzette

Inventor： LEAL, Jeffrey, S. ,  MCGRATH, Scott ,  PANGRLE, Suzette

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L24/76 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/76155 ,  H01L2224/82007 ,  H01L2224/82102 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An interconnect terminal is formed on a semiconductor die by applying an electrically conductive material in an aerosol form, for example by aerosol jet printing. Also, an electrical interconnect between stacked die, or between a die and circuitry in an underlying support such as a package substrate, is formed by applying an electrically conductive material in an aerosol form, in contact with pads on the die or on the die and the substrate, and passing between the respective pads. In some embodiments a fillet is formed at the inside corner formed by an interconnect sidewall of the die and a surface inboard from pads on an underlying feature (underlying die or support); and the electrically conductive material passes over a surface of the fillet.

Abstract translation: 互连端子通过例如通过气溶胶喷射印刷以气溶胶形式施加导电材料而形成在半导体管芯上。 而且，通过将气溶胶形式的导电材料施加在与管芯上或管芯上的焊盘接触的位置上，形成堆叠管芯之间或管芯与诸如封装衬底等下层支撑件中的电路之间的电互连， 衬底，并在相应的焊盘之间通过。 在一些实施例中，在由管芯的互连侧壁形成的内侧拐角和从下伏特征（下面的管芯或支撑件）上的焊盘向内侧的内表面形成填角; 并且导电材料通过圆角的表面。

公开(公告)号：WO2008157779A3

公开(公告)日：2009-04-16

申请号：PCT/US2008067722

申请日：2008-06-20

Applicant: VERTICAL CIRCUITS INC ,  ANDREWS LAWRENCE DOUGLAS ,  MCELREA SIMON J S ,  CASKEY TERRENCE ,  MCGRATH SCOTT ,  DU YONG

Inventor： ANDREWS LAWRENCE DOUGLAS ,  MCELREA SIMON J S ,  CASKEY TERRENCE ,  MCGRATH SCOTT ,  DU YONG

IPC: H01L27/00 ,  H01L27/10

CPC classification number: G01R1/0483 ,  H01L24/02 ,  H01L24/16 ,  H01L24/31 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2224/03

Abstract: Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g., die-to-substrate); and assemblies including a stack of at least two such devices interconnected die-to-die, or such a stack of devices electrically interconnected to underlying circuitry. Also, apparatus and methods for testing such a die.

Abstract translation: 可堆叠集成电路器件包括具有在有源（正面）侧上的互连焊盘的集成电路管芯，该管芯具有在管芯的前侧和管芯侧壁的连接处的前侧边缘， 模具的背面与侧壁的结合; 芯片还包括电连接到互连焊盘并且在模具的前侧边缘上延伸的导电迹线。 在一些实施例中，导电迹线还在侧壁上延伸，并且在一些这样的实施例中，导电迹线还在模具的背侧边缘上延伸，并且在一些这样的实施例中，导电迹线还在模具的背面延伸。 一个或两个模边可被倒角。 另外，制造这种装置的方法。 而且，包括这样的器件的组件电连接到底层电路（例如，裸片到衬底）; 以及包括至少两个这样的设备的堆叠的组件，这些设备互相连接到管芯上，或者这样一组电器互连到下面的电路。 另外，用于测试这种模具的装置和方法。

公开(公告)号：WO2008154582A3

公开(公告)日：2008-12-18

申请号：PCT/US2008/066568

申请日：2008-06-11

Applicant: VERTICAL CIRCUITS, INC. ,  MCGRATH, Scott ,  CASKEY, Terrence ,  MCELREA, Simon, J.s. ,  ANDREWS, Lawrence, Douglas ,  LIU, Zongrong

Inventor： MCGRATH, Scott ,  CASKEY, Terrence ,  MCELREA, Simon, J.s. ,  ANDREWS, Lawrence, Douglas ,  LIU, Zongrong

IPC: H01L23/02 ,  H01L21/673 ,  H01L23/28

Abstract: Fixtures for temporarily holding semiconductor die and for holding stacked die units, for application of a material such as electrical interconnection material to die edges, include a fixture frame, die or die stack supports, and a mask. Methods for applying material such as electrical interconnection material to die edges and to die stack units employ the fixtures using a mask lift-off step.

公开(公告)号：WO2008154582A2

公开(公告)日：2008-12-18

申请号：PCT/US2008066568

申请日：2008-06-11

Applicant: VERTICAL CIRCUITS INC ,  MCGRATH SCOTT ,  CASKEY TERRENCE ,  MCELREA SIMON J S ,  ANDREWS LAWRENCE DOUGLAS ,  LIU ZONGRONG

Inventor： MCGRATH SCOTT ,  CASKEY TERRENCE ,  MCELREA SIMON J S ,  ANDREWS LAWRENCE DOUGLAS ,  LIU ZONGRONG

IPC: H01L23/02 ,  H01L21/67 ,  H01L23/28

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L2221/68372 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fixtures for temporarily holding semiconductor die and for holding stacked die units, for application of a material such as electrical interconnection material to die edges, include a fixture frame, die or die stack supports, and a mask. Methods for applying material such as electrical interconnection material to die edges and to die stack units employ the fixtures using a mask lift-off step.

Abstract translation: 用于临时保持半导体管芯和用于保持堆叠的管芯单元的夹具，用于将诸如电互连材料的材料施加到管芯边缘，包括夹具框架，管芯或管芯堆叠支撑件以及掩模。 将诸如电互连材料的材料施加到模具边缘和模具堆叠单元的方法使用掩模剥离步骤使用固定装置。