Abstract:
In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.
Abstract:
Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.
Abstract:
In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion (510) of a solder ball's (140) surface is melted when the connection is formed on one structure (110) and/or when the connection is being attached to another structure (HOB). The structure (110) may be an integrated circuit, an interposer, a rigid or flexible wiring substrate, a printed circuit board, some other packaging substrate, or an integrated circuit package. In some embodiments, solder balls (140.1, 140.2) are joined by an intermediate solder ball (140i), upon melting of the latter only. Any of the solder balls (140, 140i) may have a non-solder central core (140C) coated by solder shell (140S). Some of the molten or softened solder may be squeezed out, to form a "squeeze-out" region (520, 520A, 520B, 520.1, 520.2). In some embodiments, a solder connection (210) such as discussed above, on a structure (110A), may be surrounded by a dielectric layer (1210), and may be recessed in a hole (1230) in that layer (1210), to help in aligning a post (1240) of a structure (HOB) with the connection (210) during attachment of the structures (110A, HOB). The dielectric layer (1210) may be formed by moulding. The dielectric layer may comprise a number of layers (1210.1, 1210.2), "shaved" (partially removed) to expose the solder connection (210). Alternatively, the recessed solder connections (210) may be formed using a sublimating or vapourisable material (1250), placed on top of the solder (210) before formation of the dielectric layer (1210) or coating solder balls (140); in the latter case, the solder (140C) sinks within the dielectric material (1210) upon removal of the material (1250) and subsequent reflow. The solder connections (210.1, 210.2) may be used for bonding one or more structures (HOB, HOC) (e.g. an integrated circuit die or wafer, a packaging substrate or a package) to a structure (110A) (a wiring substrate) on which a die (HOB) is flip-chip connected. The solder connections (210.1, 210.2) may differ from each other, in particular in height.
Abstract:
Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.
Abstract:
Die Erfindung betrifft ein Verfahren zur Kontaktierung einer Kontaktfläche (90) eines Halbleiterbauteils (50) und ein Elektronikmodul. Bei dem Verfahren zur Kontaktierung einer Kontaktfläche (90) eines Halbleiterbauteils (50), wird zunächst an die Kontaktfläche (90) eine sich in Richtung von der Kontaktfläche (90) weg verjüngende elektrisch leitfähige Schicht (200) gebracht und nachfolgend wird an der Schicht in zumindest einer Erstreckungsrichtung der Kontaktfläche angrenzend Isolationsmaterial (230) gebracht. Das Elektronikmodul ist insbesondere ein Leistungsmodul und umfasst ein Halbleiterbauteil mit einer Kontaktfläche (90) und mit einer Leiterbahn (225), wobei die Kontaktfläche (90) mittels eines solchen Verfahrens kontaktiert ist.
Abstract:
In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion (510) of a solder ball's (140) surface is melted when the connection is formed on one structure (110) and/or when the connection is being attached to another structure (HOB). The structure (110) may be an integrated circuit, an interposer, a rigid or flexible wiring substrate, a printed circuit board, some other packaging substrate, or an integrated circuit package. In some embodiments, solder balls (140.1, 140.2) are joined by an intermediate solder ball (140i), upon melting of the latter only. Any of the solder balls (140, 140i) may have a non-solder central core (140C) coated by solder shell (140S). Some of the molten or softened solder may be squeezed out, to form a "squeeze-out" region (520, 520A, 520B, 520.1, 520.2). In some embodiments, a solder connection (210) such as discussed above, on a structure (110A), may be surrounded by a dielectric layer (1210), and may be recessed in a hole (1230) in that layer (1210), to help in aligning a post (1240) of a structure (HOB) with the connection (210) during attachment of the structures (110A, HOB). The dielectric layer (1210) may be formed by moulding. The dielectric layer may comprise a number of layers (1210.1, 1210.2), "shaved" (partially removed) to expose the solder connection (210). Alternatively, the recessed solder connections (210) may be formed using a sublimating or vapourisable material (1250), placed on top of the solder (210) before formation of the dielectric layer (1210) or coating solder balls (140); in the latter case, the solder (140C) sinks within the dielectric material (1210) upon removal of the material (1250) and subsequent reflow. In some embodiments, the solder connections (210) may also be formed in openings (2220) in a dielectric layer (2210) (photoimageable polymer or inorganic) by solder paste printing and/or solder ball jet placement followed by reflow to let the solder sink to the bottom of the openings (2220), with possible repetition of the process and possible use of different solders in the different steps. The solder connections (210, 210.1, 210.2) may be used for bonding one or more structures (HOB, HOC) (e.g. an integrated circuit die or wafer, a packaging substrate or a package) to a structure (110A) (a wiring substrate) on which a die (HOB) is flip-chip connected. The solder connections (210, 210.1, 210.2) may differ from each other, in particular in height, which can be used for attaching a structure (HOB) with posts (1240) of different heights or for attaching two structures (HOB, HOC) in the case of a stepped form of the dielectric layer, one of the structures (HOC) being possibly placed higher than the other structure (HOB). In some embodiments, the structure (HOA) may be removed after bonding to the structures (HOB, HOC) and a redistribution layer (3210) may be formed to provide connecting lines (3220) connecting the solder connections (210) to contact pads (120R) and possibly interconnecting between the solder connections (210) and/or between the contact pads (120R).
Abstract:
Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.