公开(公告)号：WO2010020753A3

公开(公告)日：2010-06-24

申请号：PCT/GB2009001966

申请日：2009-08-11

Applicant: SEMBLANT LTD ,  HUMPHRIES MARK ROBSON ,  FERDINANDI FRANK ,  SMITH RODNEY EDWARD

Inventor： HUMPHRIES MARK ROBSON ,  FERDINANDI FRANK ,  SMITH RODNEY EDWARD

IPC: H05K3/28 ,  C12Q1/00 ,  H01H13/70 ,  H01L23/485 ,  H05K3/34

CPC classification number: H05K3/282 ,  H01H13/78 ,  H01H2215/004 ,  H01H2229/012 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/06 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45113 ,  H01L2224/45116 ,  H01L2224/4512 ,  H01L2224/45124 ,  H01L2224/45138 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45149 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/4516 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/4517 ,  H01L2224/45171 ,  H01L2224/45173 ,  H01L2224/45178 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/45644 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/8502 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/3011 ,  H05K3/222 ,  H05K3/284 ,  H05K3/328 ,  H05K2201/015 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2203/049 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/20758

Abstract: In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.

Abstract translation: 在一些实施例中，印刷电路板（PCB）包括包含绝缘材料的基板。 PCB进一步包括附着到衬底的至少一个表面的多个导电迹线。 PCB还包括沉积在基底的至少一个表面上的多层涂层。 多层涂层（i）覆盖多个导电轨道的至少一部分，并且（ii）包括至少一个由卤代烃聚合物形成的层。 所述PCB还包括至少一个电子部件，所述至少一个电子部件通过焊点连接到至少一个导电轨道，其中所述焊点焊接穿过所述多层涂层，使得所述焊点邻接所述多层涂层。

公开(公告)号：WO2008021828A3

公开(公告)日：2009-10-22

申请号：PCT/US2007075363

申请日：2007-08-07

Applicant: QUALCOMM INC ,  STEMPEL BRIAN MICHAEL ,  SMITH RODNEY WAYNE

Inventor： STEMPEL BRIAN MICHAEL ,  SMITH RODNEY WAYNE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30149 ,  G06F9/3806 ,  G06F9/3848

Abstract: In a variable-length instruction set wherein the length of each instruction is a multiple of a minimum instruction length granularity, an indication of the last granularity (i.e., the end) of a taken branch instruction is a stored in a branch target address cache (BTAC). If a branch instruction that later hits in the BTAC is predicted taken, previously fetched instructions are flushed from the pipeline beginning immediately past the indicated end of the branch instruction. This technique saves BTAC space by avoiding to the need to store the length of the branch instruction in the BTAC, and improves performance by eliminating the necessity of calculating where to begin flushing (based on the length of the branch instruction).

Abstract translation: 在每个指令的长度是最小指令长度粒度的倍数的可变长度指令集中，所采集的分支指令的最后粒度（即，结束）的指示被存储在分支目标地址高速缓存中 BTAC）。 如果预测了后来在BTAC中命中的分支指令，则先前获取的指令从直接从分支指令的指示末端开始的流水线刷新。 这种技术通过避免需要在BTAC中存储分支指令的长度来节省BTAC空间，并且通过消除计算在哪里开始刷新（基于分支指令的长度）的必要性来提高性能。

公开(公告)号：WO2009003160A1

公开(公告)日：2008-12-31

申请号：PCT/US2008/068535

申请日：2008-06-27

Applicant: QUALCOMM Incorporated ,  BADRAN-LOUCA, Serena ,  SMITH, Rodney Wayne ,  MULLVAINE, Micheal Scott

Inventor： BADRAN-LOUCA, Serena ,  SMITH, Rodney Wayne ,  MULLVAINE, Micheal Scott

IPC: G06F9/318 ,  G06F9/32 ,  G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/382 ,  G06F9/3824

Abstract: A method of expanding a conditional instruction having a plurality of operands within a pipeline processor is disclosed. The method identifies the conditional instruction prior to an issue stage and determines if the plurality of operands exceeds a predetermined threshold. The method expands the conditional instruction into a non-conditional instruction and a select instruction. The method further executes the non-conditional instruction and the select instruction in separate pipelines.

Abstract translation: 公开了一种在流水线处理器内扩展具有多个操作数的条件指令的方法。 该方法识别发布阶段之前的条件指令，并确定多个操作数是否超过预定阈值。 该方法将条件指令扩展为非条件指令和选择指令。 该方法进一步在不同的管道中执行非条件指令和选择指令。

公开(公告)号：WO2008113007A1

公开(公告)日：2008-09-18

申请号：PCT/US2008/057064

申请日：2008-03-14

Applicant: QUALCOMM Incorporated ,  SARTORIUS, Thomas Andrew ,  STEMPEL, Brian Michael ,  SMITH, Rodney Wayne

Inventor： SARTORIUS, Thomas Andrew ,  STEMPEL, Brian Michael ,  SMITH, Rodney Wayne

IPC: G06F9/318 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30196 ,  G06F9/30047 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/382

Abstract: An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.

Abstract translation: 在第一处理器指令集操作模式中执行的指令预加载指令可操作以在不同的第二指令集中正确地预加载指令。 根据指令集预加载指示符（ISPI），根据第二指令集编码对指令进行预解码。 在各种实施例中，可以在执行预加载指令之前设置ISPI，或者可以包括预加载指令或预加载目标地址的一部分。

公开(公告)号：WO2008092037A1

公开(公告)日：2008-07-31

申请号：PCT/US2008/051958

申请日：2008-01-24

Applicant: QUALCOMM INCORPORATED ,  MCLLVAINE, Michael, Scott ,  DIEFFENDERFER, James, Norris ,  NUNAMAKER, Nathan, Samuel ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne

Inventor： MCLLVAINE, Michael, Scott ,  DIEFFENDERFER, James, Norris ,  NUNAMAKER, Nathan, Samuel ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3017 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: Intermediate results are passed between constituent instructions of an expanded instruction using register renaming resources and control logic. A first constituent instruction generates intermediate results and is assigned a PRN in a constituent instruction rename table, and writes intermediate results to the identified physical register. A second constituent instruction performs a look up in the constituent instruction rename table and reads the intermediate results from the physical register. Constituent instruction rename logic tracks the constituent instructions through the pipeline, and delete the constituent instruction rename table entry and returns the PRN to a free list when the second constituent instruction has read the intermediate results.

Abstract translation: 使用寄存器重命名资源和控制逻辑，在扩展指令的组成指令之间传递中间结果。 第一组成指令生成中间结果，并在组成指令重命名表中分配PRN，并将中间结果写入所识别的物理寄存器。 第二个组成指令在组成指令重命名表中执行查询，并从物理寄存器读取中间结果。 组成指令重命名逻辑通过流水线跟踪组成指令，并删除组成指令重命名表项，并在第二组成指令读取中间结果时将PRN返回到空闲列表。

公开(公告)号：WO2008055045A1

公开(公告)日：2008-05-08

申请号：PCT/US2007/082538

申请日：2007-10-25

Applicant: QUALCOMM INCORPORATED ,  STEMPEL, Brian Michael ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

Inventor： STEMPEL, Brian Michael ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

IPC: G06F9/38

CPC classification number: G06F9/3848 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3861

Abstract: A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline stage and loads the branch history information into a first register, wherein the first register. The method further loads the branch history information into the second register during the second pipeline stage.

Abstract translation: 公开了处理分支历史信息的方法。 该方法从指令高速缓存中检索分支指令，并在多个流水线级中执行分支指令。 该方法验证分支指令已被识别。 该方法还在第一流水线阶段期间接收分支历史信息，并将分支历史信息加载到第一寄存器中，其中第一寄存器。 该方法在第二流水线阶段期间进一步将分支历史信息加载到第二寄存器中。

公开(公告)号：WO2007143508A2

公开(公告)日：2007-12-13

申请号：PCT/US2007/070111

申请日：2007-05-31

Applicant: QUALCOMM Incorporated ,  SMITH, Rodney Wayne ,  DIEFFENDERFER, James Norris ,  STEMPEL, Brian Michael ,  SARTORIUS, Thomas Andrew

Inventor： SMITH, Rodney Wayne ,  DIEFFENDERFER, James Norris ,  STEMPEL, Brian Michael ,  SARTORIUS, Thomas Andrew

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3836 ,  G06F9/3844

Abstract: A sliding-window, block-based branch target address cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the branch target address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.

Abstract translation: 滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签 第一个指令在块中。 这些块各自对应于从存储器获取的一组指令，例如I缓存。 在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。 滑动窗口，基于块的BTAC允许存储落在相同指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目 与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

公开(公告)号：WO2006130466A3

公开(公告)日：2007-11-22

申请号：PCT/US2006020440

申请日：2006-05-24

Applicant: QUALCOMM INC ,  SARTORIUS THOMAS ANDREW ,  STEMPEL BRIAN MICHAEL ,  BRIDGES JEFFREY TODD ,  DIEFFENDERFER JAMES NORRIS ,  SMITH RODNEY WAYNE

Inventor： SARTORIUS THOMAS ANDREW ,  STEMPEL BRIAN MICHAEL ,  BRIDGES JEFFREY TODD ,  DIEFFENDERFER JAMES NORRIS ,  SMITH RODNEY WAYNE

IPC: G06F9/42

CPC classification number: G06F9/3844

Abstract: A microprocessor (10) includes two branch history tables, and is configured to use a first one (48) of the branch history tables for predicting branch instructions that are hits in a branch target cache (46), and to use a second one (50) of the branch history tables for predicting branch instructions that are misses in the branch target cache (46). As such, the first branch history table (48) is configured to have an access speed matched to that of the branch target cache (46), so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table (50) thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.

Abstract translation: 微处理器（10）包括两个分支历史表，并且被配置为使用分支历史表中的第一个（48）来预测分支目标高速缓存（46）中的命中的分支指令，并且使用第二个分支指令 50）用于预测分支目标高速缓存（46）中未命中的分支指令的分支历史表。 因此，第一分支历史表（48）被配置为具有与分支目标高速缓存（46）的访问速度相匹配的访问速度，使得其预测信息相对于可能发生的早期的分支目标高速缓存命中检测而及时可用 在微处理器的指令管道中。 因此，第二分支历史表（50）仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

公开(公告)号：WO2006113420A3

公开(公告)日：2006-12-21

申请号：PCT/US2006014042

申请日：2006-04-14

Applicant: QUALCOMM INC ,  SARTORIUS THOMAS ANDREW ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  DOCKSER KENNETH ALAN ,  MCILVAINE MICHAEL SCOTT ,  SMITH RODNEY WAYNE

Inventor： SARTORIUS THOMAS ANDREW ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  DOCKSER KENNETH ALAN ,  MCILVAINE MICHAEL SCOTT ,  SMITH RODNEY WAYNE

IPC: G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

Abstract: A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

Abstract translation: 一种条件指令，被设计为接收一个或多个操作数作为输入，如果满足条件，则向目标输出对操作数执行的操作的结果，并且如果条件不满足则不提供输出，以便 它无条件地向目标提供输出。 条件指令获取目标的先前值（即由更新该目标的条件指令之前的最新指令产生的值）。 评估条件。 如果满足条件，则执行操作，并将操作结果输出到目标。 如果条件不满足，则将先前值输出到目标。 后续指令可以在条件评估之前依赖目标作为操作数源（无论是写入寄存器还是转发到指令）。

公开(公告)号：WO2006130466A2

公开(公告)日：2006-12-07

申请号：PCT/US2006/020440

申请日：2006-05-24

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas, Andrew ,  STEMPEL, Brian, Michael ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne

Inventor： SARTORIUS, Thomas, Andrew ,  STEMPEL, Brian, Michael ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne

CPC classification number: G06F9/3844

Abstract: A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.

Abstract translation: 微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令， 在分支目标缓存中丢失。 因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。 因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。