Abstract:
The invention provides a process (100) by which an integrated circuit chip (110) has a layer of overcoat material ( 130), such as a stress buffer layer, deposited on a portion of its surface prior to molding of the chip. The surface portion of the chip that is covered in the overcoat is selected based upon the configuration of the chip. For example, only those areas of the chip that are sensitive to pressure could be coated while the areas that are not sensitive to pressure are not coated. The layer of overcoat material is deposited as the deposit head (160) follows a path over the region of the surface to be covered.
Abstract:
Wire bonding operations can be facilitated through the use of metal nanoparticle compositions. Both ball bonding and wedge bonding processes can be enhanced in this respect. Wire bonding methods can include providing a wire payout at a first location from a rolled wire source via a dispensation head, contacting a first metal nanoparticle composition and a first portion of the wire payout with a bonding pad, and at least partially fusing metal nanoparticles in the first metal nanoparticle composition together to form an adhering interface between the bonding pad and the first portion of the wire payout. The adhering interface can have a nanoparticulate morphology. Wire bonding systems can include a rolled wire source, a dispensation head configured to provide a wire payout, and an applicator configured to place a metal nanoparticle composition upon at least a portion of the wire payout or upon a bonding pad.
Abstract:
In described examples, a method (400) includes applying a die attach material to a die pad of an integrated circuit (410). The die attach material is employed as a bonding material to the die pad. The method (400) includes mounting an integrated circuit die to the die pad of the integrated circuit via the die attach material (420). The method (400) includes printing an adhesion deposition material on the die attach material appearing at the interface of the integrated circuit die and the die pad of the integrated circuit to mitigate delamination between the integrated circuit die and the die pad (430).
Abstract:
In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.
Abstract:
In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.
Abstract:
The invention provides a process (100) for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip (110) based upon the configuration.
Abstract:
A method is disclosed for on-line doping of metallic connecting wire for use in integrated circuits. The method comprises the steps of: providing a bonding apparatus (70) comprising a bonding tool (40), said bonding tool having a tip (44) through which a capillary (42) runs, such that metallic connecting wire (20) may be fed through said tip (44); extending an end of the connecting wire (20) a predetermined length beyond the tip (44) of said bonding tool (40); and forming a doped area on the end of said wire by: bringing the end of said wire into contact with dopant material (52), and applying predetermined amounts of pressure, heat, and ultrasonic vibration to said end of the wire (20) for a predetermined amount of time.