公开(公告)号：WO2016032628A1

公开(公告)日：2016-03-03

申请号：PCT/US2015/039296

申请日：2015-07-07

Applicant: APPLIED MATERIALS, INC.

Inventor： KULSHRESHTHA, Prashant Kumar ,  LEE, Kwangduk Douglas ,  KIM, Bok Hoen ,  YE, Zheng John ,  BEHERA, Swayambhu Prasad ,  BALASUBRAMANIAN, Ganesh ,  ROCHA-ALVAREZ, Juan Carlos ,  CHEN, Jian J.

IPC: H01L21/683 ,  H01L21/324

CPC classification number: H01L21/6833

Abstract: Techniques are disclosed for methods and apparatuses for increasing the breakdown voltage while substantially reducing the voltage leakage of an electrostatic chuck at temperatures exceeding about 300 degrees Celsius in a processing chamber.

Abstract translation: 公开了用于增加击穿电压的方法和装置的技术，同时在处理室中大大降低了静电卡盘在超过约300摄氏度的温度下的电压泄漏。

公开(公告)号：WO2013177003A1

公开(公告)日：2013-11-28

申请号：PCT/US2013/041718

申请日：2013-05-17

Applicant: APPLIED MATERIALS, INC. ,  XU, Jingjing ,  CRUZ, Joe Griffith ,  MANNA, Pramit ,  PADHI, Deenesh ,  KIM, Bok Hoen ,  CHIN, Barry L.

Inventor： XU, Jingjing ,  CRUZ, Joe Griffith ,  MANNA, Pramit ,  PADHI, Deenesh ,  KIM, Bok Hoen ,  CHIN, Barry L.

IPC: H01L21/312 ,  H01L21/311 ,  H01L21/205

CPC classification number: G03F7/167 ,  H01L21/02118 ,  H01L21/02277 ,  H01L21/0271

Abstract: Methods and apparatus for forming a sacrificial during a novel process sequence of lithography and photoresist patterning are provided. In one embodiment, a method of processing a substrate having a resist material and an anti-reflective coating material thereon includes depositing an organic polymer layer over the surface of the substrate inside a process chamber using a CVD technique. The CVD technique includes flowing a monomer into a processing region of the process chamber, flowing an initiator into the processing region through one or more filament wires heated to a temperature between about 200C and about 450C, and forming the organic polymer layer. In addition, the organic polymer layer is ashable and can be removed from the surface of the substrate when the resist material is removed from the surface of the substrate.

Abstract translation: 提供了在光刻和光致抗蚀剂图案化的新工艺序列期间形成牺牲的方法和装置。 在一个实施例中，一种在其上处理具有抗蚀剂材料和抗反射涂层材料的衬底的方法包括使用CVD技术在处理室内的衬底的表面上沉积有机聚合物层。 CVD技术包括使单体流入处理室的处理区域，通过加热到约200℃至约450℃之间的温度的一根或多根细丝丝将引发剂流入加工区域，并形成有机聚合物层。 另外，当从基板的表面去除抗蚀剂材料时，有机聚合物层是可灰化的，并且可以从基板的表面去除。

公开(公告)号：WO2012154429A2

公开(公告)日：2012-11-15

申请号：PCT/US2012/035659

申请日：2012-04-27

Applicant: APPLIED MATERIALS, INC. ,  LEE, Kwangduk D. ,  RATHI, Sudha ,  SANKARAKRISHNAN, Ramprakash ,  SEAMONS, Martin J. ,  JAMIL, Irfan ,  KIM, Bok Hoen

Inventor： LEE, Kwangduk D. ,  RATHI, Sudha ,  SANKARAKRISHNAN, Ramprakash ,  SEAMONS, Martin J. ,  JAMIL, Irfan ,  KIM, Bok Hoen

IPC: H01L21/3065

CPC classification number: H01L21/31122 ,  H01L21/0206 ,  H01L21/31144

Abstract: Embodiments of the invention generally relate to methods of dry stripping boron-carbon films. In one embodiment, alternating plasmas of hydrogen and oxygen are used to remove a boron-carbon film. In another embodiment, co-flowed oxygen and hydrogen plasma is used to remove a boron-carbon containing film. A nitrous oxide plasma may be used in addition to or as an alternative to either of the above oxygen plasmas. In another embodiment, a plasma generated from water vapor is used to remove a boron-carbon film. The boron-carbon removal processes may also include an optional polymer removal process prior to removal of the boron-carbon films. The polymer removal process includes exposing the boron-carbon film to NF 3 to remove from the surface of the boron-carbon film any carbon-based polymers generated during a substrate etching process.

Abstract translation: 本发明的实施方案一般涉及干燥汽提硼 - 碳膜的方法。 在一个实施方案中，使用氢和氧的交替等离子体去除硼 - 碳膜。 在另一个实施方案中，使用共流氧和氢等离子体去除含硼碳膜。 除了作为上述氧等离子体中的任一种之外，还可以使用一氧化二氮等离子体。 在另一个实施方案中，使用由水蒸气产生的等离子体来除去硼 - 碳膜。 在除去硼 - 碳膜之前，硼 - 碳去除方法还可以包括任选的聚合物去除方法。 聚合物去除方法包括将硼 - 碳膜暴露于NF3以从硼 - 碳膜的表面除去在基板蚀刻工艺期间产生的任何碳基聚合物。

公开(公告)号：WO2008091900A1

公开(公告)日：2008-07-31

申请号：PCT/US2008/051715

申请日：2008-01-22

Applicant: APPLIED MATERIALS, INC. ,  NOORI, Atif ,  SCHMITT, Francimar ,  LAKSHMANAN, Annamalai ,  KIM, Bok Hoen ,  ARGHAVANI, Reza

Inventor： NOORI, Atif ,  SCHMITT, Francimar ,  LAKSHMANAN, Annamalai ,  KIM, Bok Hoen ,  ARGHAVANI, Reza

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/7682 ,  H01L21/76885 ,  H01L2221/1036

Abstract: Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately 1. The air gap may generally be formed by depositing a sacrificial material between the respective conductive elements, depositing a porous layer over the conductive elements and the sacrificial material, and then stripping the sacrificial material out of the space between the respective conductive elements through the porous layer, which leaves an air gap between the respective conductive elements. The sacrificial material may be, for example, a polymerized alpha terpinene layer, the porous layer may be, for example, a porous carbon doped oxide layer, and the stripping process may utilize a UV based curing process, for example.

Abstract translation: 本发明的实施例通常提供了在半导体器件的导电元件之间形成空气间隙的方法，其中气隙的介电常数约为1.气隙通常可以通过在相应的导电元件之间沉积牺牲材料而形成 在导电元件和牺牲材料之上沉积多孔层，然后通过多孔层将牺牲材料从相应的导电元件之间的空间中剥离，该多孔层留下各导电元件之间的气隙。 牺牲材料可以是例如聚合的α萜品烯层，多孔层可以是例如多孔碳掺杂的氧化物层，并且剥离过程可以使用例如基于UV的固化方法。

公开(公告)号：WO2008024566A2

公开(公告)日：2008-02-28

申请号：PCT/US2007/073360

申请日：2007-07-12

Applicant: APPLIED MATERIALS, INC. ,  LAKSHMANAN, Annamalai ,  NGUYEN, Vu Nt ,  PARK, Sohyun ,  BALASUBRAMANIAN, Ganesh ,  REITER, Steven ,  KIYOHARA, Tsutomu ,  SCHMITT, Francimar ,  KIM, Bok Hoen

Inventor： LAKSHMANAN, Annamalai ,  NGUYEN, Vu Nt ,  PARK, Sohyun ,  BALASUBRAMANIAN, Ganesh ,  REITER, Steven ,  KIYOHARA, Tsutomu ,  SCHMITT, Francimar ,  KIM, Bok Hoen

IPC: H01L21/473

CPC classification number: C23C16/4404 ,  C23C16/0245 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/3185

Abstract: The present invention generally provides an apparatus and method for reducing defects on films deposited on semiconductor substrates. One embodiment of the present invention provides a method for depositing a film on a substrate. The method comprises treating the substrate with a first plasma configured to reduce pre-existing defects on the substrate, and depositing a film comprising silicon and carbon on the substrate by applying a second plasma generated from at least one precursor and at least one reactant gas.

Abstract translation: 本发明通常提供一种用于减少沉积在半导体衬底上的薄膜上的缺陷的装置和方法。 本发明的一个实施方案提供了一种在基材上沉积膜的方法。 该方法包括用配置成减少衬底上预先存在的缺陷的第一等离子体处理衬底，以及通过施加由至少一种前体和至少一种反应气体产生的第二等离子体将包含硅和碳的膜沉积在衬底上。

公开(公告)号：WO2017100136A1

公开(公告)日：2017-06-15

申请号：PCT/US2016/065007

申请日：2016-12-05

Applicant: APPLIED MATERIALS, INC.

Inventor： YE, Zheng John ,  HANAWA, Hiroji ,  ROCHA-ALVAREZ, Juan Carlos ,  MANNA, Pramit ,  TSIANG, Michael Wenyoung ,  KO, Allen ,  WANG, Wenjiao ,  LIN, Yongjing ,  KULSHRESHTHA, Prashant Kumar ,  HAN, Xinhai ,  KIM, Bok Hoen ,  LEE, Kwangduk Douglas ,  NARASIMHA, Karthik Thimmavajjula ,  DUAN, Ziqing ,  PADHI, Deenesh

IPC: H01L21/683 ,  H05H1/46 ,  H01J49/10 ,  H01L21/687

CPC classification number: H01L21/6833 ,  C23C16/458 ,  C23C16/4586 ,  C23C16/505 ,  C23C16/509 ,  H01J37/32091 ,  H01L21/02274 ,  H01L21/0262 ,  H01L21/28556

Abstract: Techniques are disclosed for methods and apparatuses of an electrostatic chuck suitable for operating at high operating temperatures. In one example, a substrate support assembly is provided. The substrate support assembly includes a substantially disk-shaped ceramic body having an upper surface, a cylindrical sidewall, and a lower surface. The upper surface is configured to support a substrate thereon for processing the substrate in a vacuum processing chamber. The cylindrical sidewall defines an outer diameter of the ceramic body. The lower surface is disposed opposite the upper surface. An electrode is disposed in the ceramic body. A circuit is electrically connected to the electrode. The circuit includes a DC chucking circuit, a first RF drive circuit, and a second RF dive circuit. The DC chucking circuit, the first RF drive circuit and the second RF drive circuit are electrically coupled with the electrode..

Abstract translation: 公开了适用于在高操作温度下操作的静电吸盘的方法和装置的技术。 在一个例子中，提供了衬底支撑组件。 基板支撑组件包括具有上表面，圆柱形侧壁和下表面的大致盘形陶瓷体。 上表面被构造成支撑其上的衬底以用于在真空处理室中处理衬底。 圆柱形侧壁限定了陶瓷体的外径。 下表面与上表面相对设置。 电极设置在陶瓷体中。 电路电连接到电极。 该电路包括DC夹持电路，第一RF驱动电路和第二RF潜水电路。 DC夹持电路，第一RF驱动电路和第二RF驱动电路与电极电耦合。

公开(公告)号：WO2015134120A1

公开(公告)日：2015-09-11

申请号：PCT/US2015/011716

申请日：2015-01-16

Applicant: APPLIED MATERIALS, INC.

Inventor： HA, Sungwon ,  LEE, Kwangduk Douglas ,  BALASUBRAMANIAN, Ganesh ,  ROCHA-ALVAREZ, Juan Carlos ,  SEAMONS, Martin Jay ,  DUAN, Ziqing ,  YE, Zheng John ,  KIM, Bok Hoen ,  JING, Lei ,  LE, Ngoc ,  MUKUTI, Ndanka

IPC: H01L21/3065 ,  H01L21/683

CPC classification number: C23C16/45565 ,  C23C16/4401 ,  C23C16/4585 ,  C23C16/5096 ,  H01J37/32091 ,  H01J37/32449

Abstract: Embodiments described herein relate to a faceplate for improving film uniformity. A semiconductor processing apparatus includes a pedestal, an edge ring and a faceplate having distinct regions with differing hole densities. The faceplate has an inner region and an outer region which surrounds the inner region. The inner region has a greater density of holes formed therethrough when compared to the outer region. The inner region is sized to correspond with a substrate being processed while the outer region is sized to correspond with the edge ring.

Abstract translation: 本文所述的实施例涉及一种用于提高膜均匀性的面板。 半导体处理装置包括具有不同孔洞密度区域的基座，边缘环和面板。 面板具有内部区域和围绕内部区域的外部区域。 当与外部区域相比时，内部区域具有通过其形成的更大密度的孔。 内部区域的尺寸设置成对应于正在处理的基底，而外部区域的尺寸被设计成与边缘环相对应。

公开(公告)号：WO2013101423A1

公开(公告)日：2013-07-04

申请号：PCT/US2012/068087

申请日：2012-12-06

Applicant: APPLIED MATERIALS, INC. ,  HAN, Xinhai ,  RAJAGOPALAN, Nagarajan ,  XUAN, Guangchi ,  ZHOU, Jianhua ,  LI, Jigang ,  SHAIKH, Shahid ,  REILLY, Patrick ,  NOWAK, Thomas ,  ROCHA-ALVAREZ, Juan Carlos ,  PARK, Heung Lak ,  KIM, Bok Hoen

Inventor： HAN, Xinhai ,  RAJAGOPALAN, Nagarajan ,  XUAN, Guangchi ,  ZHOU, Jianhua ,  LI, Jigang ,  SHAIKH, Shahid ,  REILLY, Patrick ,  NOWAK, Thomas ,  ROCHA-ALVAREZ, Juan Carlos ,  PARK, Heung Lak ,  KIM, Bok Hoen

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/66833 ,  C23C16/24 ,  C23C16/345 ,  C23C16/401 ,  C23C16/505 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L27/11582 ,  H01L29/7926

Abstract: Methods are provided for depositing a stack of film layers for use in vertical gates for 3D memory devices, by depositing a sacrificial nitride film layer at a sacrificial film deposition temperature greater than about 550 °C; depositing an oxide film layer over the nitride film layer, at an oxide deposition temperature of about 600 °C. or greater; repeating the above steps to deposit a film stack having alternating layers of the sacrificial films and the oxide films; forming a plurality of holes in the film stack; and depositing polysilicon in the plurality of holes in the film stack at a polysilicon process temperature of about 700 °C. or greater, wherein the sacrificial film layers and the oxide film layers experience near zero shrinkage during the polysilicon deposition. Flash drive memory devices may also be made by these methods.

Abstract translation: 提供了用于通过在大于约550℃的牺牲膜沉积温度下沉积牺牲氮化物膜层来沉积用于3D存储器件的垂直栅极中的薄膜层堆叠的方法; 在氧化物沉积温度约600℃下在氮化物膜层上沉积氧化膜层。 或更大; 重复上述步骤以沉积具有交替层的牺牲膜和氧化物膜的膜堆叠; 在薄膜叠层中形成多个孔; 以及在约700℃的多晶硅工艺温度下在所述膜堆叠中的多个孔中沉积多晶硅。 或更大，其中牺牲膜层和氧化物膜层在多晶硅沉积期间经历接近零收缩。 也可以通过这些方法制造闪存驱动器存储器件。

公开(公告)号：WO2011137059A2

公开(公告)日：2011-11-03

申请号：PCT/US2011/033750

申请日：2011-04-25

Applicant: APPLIED MATERIALS, INC. ,  YU, Hang ,  PADHI, Deenesh ,  CAI, Man-Ping ,  YOSHIDA, Naomi ,  MIAO, Li Yan ,  CHENG, Siu F. ,  SHAIKH, Shahid ,  PARK, Sohyun ,  PARK, Heung Lak ,  KIM, Bok Hoen

Inventor： YU, Hang ,  PADHI, Deenesh ,  CAI, Man-Ping ,  YOSHIDA, Naomi ,  MIAO, Li Yan ,  CHENG, Siu F. ,  SHAIKH, Shahid ,  PARK, Sohyun ,  PARK, Heung Lak ,  KIM, Bok Hoen

IPC: H01L21/205 ,  H01L21/027

CPC classification number: H01L21/02115 ,  C23C16/26 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338

Abstract: Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer for improved stack defectivity on a substrate is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less; and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater to form the composite amorphous carbon layer.

Abstract translation: 本文描述的实施例涉及用于图案化和蚀刻半导体衬底中的特征的材料和工艺。 在一个实施例中，提供了形成用于提高衬底缺陷率的复合非晶碳层的方法。 该方法包括将基板定位在处理室中，将烃源气体引入处理室中，将稀释源气体引入处理室，将等离子体起始气体引入处理室，在处理室中产生等离子体， 在所述基板上形成无定形碳起始层，其中所述烃源气体的体积流量与稀释剂源气体流量比为1:12以下; 以及在所述无定形碳起始层上形成块状无定形碳层，其中用于形成所述块状无定形碳层的烃源气体具有以1:6或更大的稀释剂源气体流量的体积流量，以形成所述复合非晶体 碳层。

公开(公告)号：WO2008094792A1

公开(公告)日：2008-08-07

申请号：PCT/US2008/051731

申请日：2008-01-22

Applicant: APPLIED MATERIALS, INC. ,  DEMOS, Alexandros T. ,  XIA, Li-Qun ,  KIM, Bok Hoen ,  WITTY, Derek R. ,  M'SAAD, Hichem

Inventor： DEMOS, Alexandros T. ,  XIA, Li-Qun ,  KIM, Bok Hoen ,  WITTY, Derek R. ,  M'SAAD, Hichem

IPC: H01L23/482 ,  H01L21/469

CPC classification number: H01L21/7682 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/3146 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76811 ,  H01L21/76835 ,  H01L2221/1047 ,  Y10S438/931

Abstract: Methods are provided for forming a structure that includes an air gap In one embodiment, a method is provided for forming a damascene structure compnses depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen -containing matenal, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature defintion in the organic and dielectric constant layer, filling the feature definition with a conductive material, depositing a mask layer on the organic layer, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive matenal.

Abstract translation: 提供用于形成包括气隙的结构的方法。在一个实施例中，提供了一种用于形成镶嵌结构的方法，其包括通过包括使有机硅化合物和致孔剂提供前体反应的方法沉积多孔低介电常数层， 致孔剂材料，并且除去至少一部分含致孔剂的马氏体，通过使造孔剂提供前体反应，在有机和介电常数层中形成特征定义，将有机层沉积在多孔低介电常数层上，填充 具有导电材料的特征定义，在有机层上沉积掩模层，在掩模层中形成孔以暴露有机层，通过孔去除部分或全部有机层，以及形成邻近导电的气隙 matenal。