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    Improved semiconductor package
    131.
    发明公开
    Improved semiconductor package 失效
    改进的半导体封装

    公开(公告)号：EP0139029A1

    公开(公告)日：1985-05-02

    申请号：EP83110436.9

    申请日：1983-10-19

    申请人： Olin Corporation

    发明人： Butt, Sheldon H.

    IPC分类号： H01L23/48 ,  H01L23/14

    CPC分类号： H01L23/047 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3672 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2224/45099

    摘要： A chip carrier 90 and a process of assembling a chip carrier are disclosed. The carrier used for mounting a chip comprises a copper or copper base alloy component 92 having a thin interface layer or refractory oxide layer 93 on a surface thereof. The surface and the interface or oxide layer have an indentation formed therein for receiving the chip 102. A metallic circuit pattern 98 for electrical connection to the chip is bonded to the interface or oxide layer and insulated from the copper or copper base alloy by the interface layer or refractory oxide layer. A seal 104 is provided for enclosing the chip to the indentation. Another embodiment of the invention includes a circuit board structure comprising a circuit board device 24 having a first coefficient of thermal expansion. A chip carrier 90 is provided having a second coefficient thermal expansion of substantially the same value as the first coefficient of thermal expansion. The chip carrier has electrical leads 100 soldered to the circuit board whereby thermal cycling of the circuit board structure does not substantially stress the bond between the solder, leads and circuit board. Other embodiments of the present invention include both leadless and leaded hermetic semiconductor packages and innovative relationships between the packages and printed circuit boards.

    摘要翻译： 公开了芯片载体90和组装芯片载体的过程。 用于安装芯片的载体包括在其表面上具有薄界面层或难熔氧化物层93的铜或铜基合金部件92。 表面和界面或氧化物层具有在其中形成的用于接纳芯片102的压痕。用于与芯片电连接的金属电路图案98被结合到界面或氧化物层并通过界面与铜或铜基合金绝缘 层或耐火氧化物层。 提供密封件104用于将芯片封闭到凹槽中。 本发明的另一实施例包括电路板结构，其包括具有第一热膨胀系数的电路板装置24。 提供具有与第一热膨胀系数基本上相同的值的第二系数热膨胀的芯片载体90。 芯片载体具有焊接到电路板的电引线100，由此电路板结构的热循环基本上不会对焊料，引线和电路板之间的结合造成应力。 本发明的其他实施例包括无引线和引线密封半导体封装以及封装和印刷电路板之间的创新关系。

    Improved semiconductor package
    134.
    发明公开
    Improved semiconductor package 失效
    Halbleiterpackung。

    公开(公告)号：EP0092019A2

    公开(公告)日：1983-10-26

    申请号：EP83100492.4

    申请日：1983-01-20

    申请人： Olin Corporation

    发明人： Butt, Sheldon H.

    IPC分类号： H01L23/04 ,  H01L23/14 ,  H01L23/48

    CPC分类号： H05K1/053 ,  H01L23/047 ,  H01L23/142 ,  H01L23/49537 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H05K1/0306 ,  H05K3/42 ,  H05K2201/0382 ,  H05K2203/068 ,  H01L2924/00 ,  H01L2224/45099

    摘要： A chiop carrier 90 and a process of assembling a chip carrier are disclosed. The carrier used for mounting a chip comprises a copper or copper base alloy component 92 having a thin refractory oxide layer 93 on a surface thereof. The surface and the oxide layer have an indentation formed therein for receiving the chip 102. A metallic circuit pattern 98 for electrical connection to the chip is bonded to the oxide layer and insulated from the copper or copper base alloy by the refractory oxide layer. A seal 104 is provided for enclosing the chip to the indentation. Another embodiment of the Invention includes a circuit board structure comprising a circuit board device 24 having a first coefficient of thermal expansion. A chip carrier 90 is provided having a second coefficient thermal expansion of substantially the same value as the first coefficient of thermal expansion. The chip carrier has electrical leads 100 soldered to the circuit board whereby thermal cycling of the circuit board structure does not substantially stress the bond between the solder, leads and circuit board. Other embodiments of the present invention include both leadless and leaded hermetic semiconductor packages and innovative relationships between the packages and printed circuit boards.

    摘要翻译： 本发明公开了一种飞梭载体90和组装芯片载体的方法。 用于安装芯片的载体包括在其表面上具有薄的难熔氧化物层93的铜或铜基合金组分92。 表面和氧化物层在其中形成有用于接收芯片102的凹陷。用于与芯片电连接的金属电路图案98结合到氧化物层，并通过难熔氧化物层与铜或铜基合金绝缘。 提供密封件104用于将芯片封装到压痕。 本发明的另一实施例包括电路板结构，其包括具有第一热膨胀系数的电路板装置24。 提供了具有与第一热膨胀系数基本相同的值的第二系数热膨胀的芯片载体90。 芯片载体具有焊接到电路板的电引线100，由此电路板结构的热循环基本上不会压迫焊料，引线和电路板之间的结合。 本发明的其它实施例包括无引线和有铅密封半导体封装以及封装和印刷电路板之间的创新关系。